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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

  

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FPGA to ARM7 shared memory concept via wishbone.   [6 Articles]

djam...@gmail.com - Aug 24 2010
Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ... FPGA to ARM7 shared memory concept via wishbone.

Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N) -

mani...@gmail.com - May 24 2010
> > Hello, > > Does somebody work with DC-VIDEO-TVP5146N Altera kit > > (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? > > I try to connect DC-V... Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N) -

Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)

gmdi...@gmail.com - May 13 2010
Hello, Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? I try to connect DC-VIDEO-TVP5146N to DK-NI... Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)

Implementation of LRU algo in verilog   [7 Articles]

ruchi_rastogi25 - Apr 10 2010
Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating... Implementation of LRU algo in verilog

Visit my Netlog profile

MOhan Kabadi - Apr 9 2010
Hey, I have created a Netlog profile with my pictures, videos, blogs and events and I want to add you as a friend so you can see it. You first need to register on Netlog! When y... Visit my Netlog profile

Beginning with FPGAs   [3 Articles]

rtstofer - Jan 14 2010
Altera and Arrow have joint ventured a neat little Hitex USB based FPGA evaluation USB stick for $49 http://www.altera.com/b/nios-bemicro-evaluation-kit.html?GSA_pos=3&WT.oss_r=... Beginning with FPGAs

problem on coding tcp/ip   [9 Articles]

Prakash - Jan 12 2010
hello everyone i'm undergraduate student, doing my 4 yr bachelor in electronics and communication engineering. currently i'm holding my final year project on implementation of FPG... problem on coding tcp/ip

Using DDR RAM   [42 Articles]

rtstofer - Oct 18 2009
I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core. So I started over at OpenCores and downloaded a DDR co... Using DDR RAM

Altera license MIPS32 architecture   [2 Articles]

jalobaba - Oct 8 2009
You all might be interested in this announcement: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=220301386 ------------------------------------ To post a ... Altera license MIPS32 architecture

Alpha source code

Zarandi - Jul 27 2009
Dear All, Do any of you have or know HDL source code (Verilog or VHDL) of any Alpha processors? Regards, --Hamid [Non-text portions of this message have been removed] ---... Alpha source code
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