FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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rtstofer - Oct 18 2009
I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core.
So I started over at OpenCores and downloaded a DDR co... 
jalobaba - Oct 8 2009
You all might be interested in this announcement:
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=220301386
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ruchi_rastogi25 - Aug 2 2009
Hi all,
I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating... 
Zarandi - Jul 27 2009
Dear All,
Do any of you have or know HDL source code (Verilog or VHDL) of any Alpha processors?
Regards,
--Hamid
[Non-text portions of this message have been removed]
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h_zarandi - Jul 27 2009
Dear all,
Do any of you have or know any HDL core of any Alpha processors?
regards,
--Hamid
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h_zarandi - Jul 27 2009
Dear Ben,
Do you have HDL source code of Alpha processor?
/hamid
--- In f...@yahoogroups.com, "Ben A. Abderazek" wrote:
>
> Hello Helpers,
>
> Does any one have ... 
abhishek kumar - Apr 6 2009
sir I have to design a CPU in VHDL . I have designed each block like alu,register,control,memory separately but i am not able to interface each . All block are working but all are ... 
potxoka3a - Apr 3 2009
hi
I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA=
with VHDL, analyzing and changing a few signs of a data bus of 20 signals =
(transceiver). The... 
abhishek kumar - Apr 1 2009
sir I need the source code of 8 bit CPU in vhdl language, plz send me soon
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