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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "virtex"
Virtex-II released
Mike Butts - Jan 15 2001
There's an avalanche of Virtex-II summaries, datasheets and app notes
released today on their web site.
For example, the XC2V6000 has 76K logic cells, 144 18Kbi... 
Spartan2 or Virtex specific xr16/xr32 [3 Articles]
Christian Plessl - Mar 7 2001
Hi everybody.
Jan Gray announced, that he we wants to "port" the XSOC system to Xilinx
Spartan resp. Virtex architecture. As most of the architecture will be th... Virtex board [2 Articles]
Sumeet Suri - Feb 6 2002
Hey guys,
I am looking at buyin a Virtex E board or a Virtex 2 board with very high gate density ( 2 million and more).
The board must also have a Ethernet Inter... help me about comparing time consumption of virtex-II and pentiumIII in fft implementation
shahram ghaebi - Dec 9 2002
hi
i want to implement 1024 point fft on fpga so
i want to know what way is best ?
1-implement it on virtex-II?
2-programming on pentium with matlab?
(time co... Number of BUFG in Xilinx Virtex BG432 device.
Young-Su Kwon - Apr 4 2001
Does anybody know how many number of BUFG cell
can be used in Virtex BG432 device?
------------------------------
Young-Su Kwon
Ph. D student, KAIST
... New Development Board from Insight
Will Cummings - Oct 25 2000
Jan,
I thought this was relevant. Hope you don't mind my "advertising" our new
board here.
Will
Insight To Announce New Virtex-E Development Board ... RE: format of the Xilinx bit file
Aare Tali - May 11 2002
> -----Original Message-----
> From: stuckatone [mailto:]
> Sent: Wednesday, May 08, 2002 9:26 AM
> To:
> Subject: [fpga-cpu] format of the Xilinx bit file
>... "The Knowledge": Virtex circuit tricks for add/mux
Jan Gray - Nov 12 2000
Many datapath circuits consist of an adder followed by a mux. For example,
one appears in the PC/adder unit of xr16 -- next PC is either PC +
PC-increment or is the... RE: Timings [2 Articles]
Jan Gray - Oct 19 2001
> Do you think it's possible to get this working >50MHz after
> floorplanning, or is it not worth the effort ?
I can't speak for Virtex-II, with its active (buf... RE: Sound on an FPGA? [4 Articles]
Jan Gray - Apr 2 2002
See also
XAPP154: Virtex Synthesizable Delta-Sigma DAC,
http://www.xilinx.com/xapp/xapp154.pdf,
and its partner,
XAPP155: Virtex Analog to Digital Converte... Re: Help please [7 Articles]
Vikram Chandrasekhar - Aug 2 2002
I assume that you are targetting it towards a FPGA. Xilinx, for example
provides really neat clock buffers (CLKDLL in Virtex FPGA's/DCM in
Virtex-2) that can multip... Regarding the core-gen
Vikram Chandrasekhar - Jun 8 2002
Hello all,
I am trying to use an IP-CORE Virtex multiplier block for my design.
The CORE GEN is targetted to a Virtex-2 FPGA, has an output latency of
4 cyc... PCI implementation using Xilinx FPGA [4 Articles]
wilton peter - Oct 9 2002
Dear All,
I'm considering to design a PCI interface card using Xilinx FPGA and now I'm choosing the suitable chips. Would appreciate very much could anyone here he... [Fwd: KCPSM]
Ben Franchuk - Dec 4 2000
Ken Chapman wrote:
>
> Dear Mr Franchuk,
>
> I have just been shown an email in which you speak about small CPUs on
> FPGAs and I thought you might like to ... free Xilinx FPGA dev tools on the way
Jan Gray - Oct 2 2000
"XILINX ADDS FPGA SUPPORT TO FREE WEB DESIGN TOOLS"
See http://www.xilinx.com/prs_rls/webfpga.html:
"Xilinx, Inc. today announced full support of the enti... Re: What are peoples opinion of the Altera Nios Processor? [2 Articles]
Christian Plessl - Mar 18 2003
> I'll be writing a paper in the next few weeks: a survey of commercially and
> freely available 32-bit RISC IP cores.
Interssting. You may post a link to the pa... Re: FPGA speeds and costs (was RAM for XSOC)
Mike Butts - Mar 25 2000
Tom Cantrell wrote:
> I seem to recall that Jan said his design simulated with better performance
> on Spartan than XC4xxx - can't remember the explanation for the ... Power optimization at Code level? [2 Articles]
gutty19 - Mar 27 2005
Hi,
I am concerend more on Virtex fpgas. Are there any special way of
planning the architecture of a fpga design which would reduce the
power consumption (for eg. re... RE: D-Latch vs Flip-flop
Jan Gray - Jun 17 2001
Good thinking. I have gone down that path myself. Note two things.
1. In the XC4000-derived architectures, the LUT RAM and the FFs-or-latches
have independent cl... Question reg. using BUFGCE in Virtex-II
Vikram Chandrasekhar - Aug 7 2002
Hi ,
I have a question regarding using the BUFGCE module in the Xilinx Virtex
II FPGA for disabling the global clock buffer for turning off idle
functional ... Using Altera software to lay out/floorplan Xilinx part ?
TD - Apr 4 2001
Is it possible to synthesize you design into Xilinz part, let's say
Virtex II, and using maxplus or quartus to layout/floorplan ? Thanks.
... Virtex-4 EDK7.1 and VGA display
kris...@... - Jul 8 2005
Hi,
I am trying to drive the VGA display on a ML402 board using EDK7.1i and ISE7.1. I am basically using the ML40x reference design provided by Xilinx.
The problem is that ... Where to get FPGA Development Kit [3 Articles]
Friedhelm Rünz - Feb 11 2002
I'm looking for a FPGA development kit with at least a Virtex 400.
It should contain SDRAM, SRAM, FLASH, DAC, VGA, PS/2, USB, JTAG, UART...
Actually I was intereste... BRAM speed [was: Multi-context processor]
Tommy Thorn - Dec 4 2006
I just started playing with Xilinx Spartan 3E (speed grade -4) and I was appalled to find that even with extreme care can I only run the BRAMs at 170 MHz. Anything realistic and th... Strict P&R in Xilinx chips [2 Articles]
Eric Laforest - Dec 2 2001
Is it possible to generate a design that is explicitely placed and routed?
(ie: this reg goes here, uses these tristate lines up to here, etc...)
I presume that ... tutorials about soft-core processors
Dries Driessens - Dec 8 2003
Dear,
maybe interesting information for people who are new at softcore
processors and busses.
during the course of our research project "embedded system des... arithmetic circuits [2 Articles]
ANI . - Aug 14 2002
Hi,
I'm currently working with a virtex FPGA and I'm studying the advantages and disadvantages of a such arithmetic circuit. For instance:
full adder x CSA... XSV Board [6 Articles]
Steve - Aug 3 2000
Hi all! I recently purchased the new XESS XSV board that contains a Virtex
FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project, but
I'm having som... Bit Stream Arithmetic
Sagar Sen - Mar 13 2003
Hi Mr. Jan Gray
I'm trying to implement a systolic array on a Virtex FPGA. The number
of inputs is limited, hence I decided to use deterministic bit stream
a... Multiplying
Kolja Sulimma - Apr 11 2001
Hi!
After my above tirades about NOT using multiplies, here is what I think you should
do, if you really want to do DSP in an FPGA:
Build a vector CPU.
... Re: Initial block ram contents
Christian Plessl - Jan 3 2002
> How do I initialize the block ram contents without going through the
> PAR process every time ? Could someone please point me to more info.
What kind of devic... regarding CAM design
Jin Yan - Mar 10 2003
Hi,all,
I am considering design of CAM with Virtex. Xilinx
gave out some application notes regarding CAM design.
But i have some questions,
1. What are the ... Porting xr16 to XSV-300 [2 Articles]
- Nov 28 2000
I'm attempting to port the xr16 processor to an XSV-300 prototyping
board. However, since this particular board has no way to preload
SRAM I'm rather stuck. I was w... XSOC/xr16 running on Virtex
Jan Gray - Oct 11 2000
This afternoon I resumed the Virtex port of XSOC/xr16/xr32 and am now
(finally) running XSOC/xr16 in my XESS XSV-300 prototyping board.
Today's work involved sev... RE: MicroBlaze
Jan Gray - Apr 9 2001
Thank you very much, Mike.
Let us not forget Philip Freidin's seminal RISC4005. It took Xilinx a
decade to come to appreciate soft processor cores.
> Your x... RE: Re: new paper on FPGA CPU and SoC design at www.fpgacpu.org
Jan Gray - Jan 5 2001
> From: [mailto:]
>
> because I will design a SoPC,
> so I want to learn something from this paper,
> but I found there are so many abbreviations,some I couldn... ASB to PCI bridge [5 Articles]
wilton peter - Mar 5 2003
Hello All,
Could anyone here tell me where I can find some vode on the AMBA/ASB to PCI bridge? I'm using the CARMeN-Xilinx v3 board. There is an ARM7 processor and... Re: FPGA Development Board Needed
Ed Corter - Nov 14 2001
There are boards and they would be sold as is. I am
sure theat they would run the standard SW test of all
peripherals and at the least establish that the JTAG
cha... Paul Metzgen on multiplexers and the NIOS II pipeline [2 Articles]
Tommy Thorn - Jul 29 2007
Trying to understand the LAB wide sload and sclear signals better, I happend
upon this gem by Paul Metzgen: http://www.cs.tut.fi/soc/Metzgen04.pdf (I wish I had attended this tal...