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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "xsoc"
issue: xsoc\Xsoc.pdf generates "File does not begin with %PDF-" [2 Articles]
Dan Crowl - Mar 16 2000
Nice piece of work, Jan, thanks.
trivial issues:
a. Downloaded the distribution to NT4 system and installed, compiled and
simulated the demos [no board yet] ac... 
FPGA build problem [2 Articles]
Leon Heller - May 24 2000
Hello all,
I've just been trying to build the latest release (schematic, as I don't
have Verilog) using Foundation 1.5i, without success. The log file is
app... Re: issue: xsoc\Xsoc.pdf generates "File does not begi n with %PDF-" [2 Articles]
Hernan Dario Sanchez Echeverri - Mar 17 2000
Hi.
The xsoc/xsoc.pdf file is the control file of the "Xilinx Project Manager"
project. They use the same PDF extension. The real PDF files are in the
DOC dire... Xilinx SpartanXL [4 Articles]
- Mar 22 2000
I'm going to have a go at putting XSOC onto a little SpartanXL proto
board I designed a few months ago. Until now I've been using the
XCS05XL, which isn't big enoug... issue #13: XSOC problems on XS40 v1.4+ boards (with 128 KB ram)
Jan Gray, Gray Research LLC - Mar 18 2000
Issue reported, understood, fixed, but fix not yet verified nor dropped to
web site.
Effect of fix is 1) new version of XSOC.sch, 2) new flavors of UCF files and... RE: 16-bit CPU with C complier?
Jan Gray - Nov 1 2002
The XSOC/xr16 Kit is a free for non-commercial use (see
www.fpgacpu.org/xsoc/LICENSE.html) Verilog 16-bit pipelined CPU with a C
compiler. See www.fpgacpu.org/xsoc/... XSOC using latest Xilinx WebPack 6.2i
saibal_das - Sep 7 2004
Please let me know if there exist any information about using XSOC
BETA 093 with Xilinx WebPack 6.2i such as how-to guide and project
files ( *.npl )
Thanks,... RE: Xilinx bitgen problem [3 Articles]
Jan Gray - Jan 5 2001
It appears that you are using a net, clk, that has no driver. I assume you
hope to use an external clock signal. You must bring it into the device
(and reflect that... Xsoc 16bit RISC [3 Articles]
shibashish patel - Jan 5 2004
We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain the test-bench written for the sam... XSOC and XS-50 or BurchEd B5-X300
rtstofer - Jul 17 2003
It would appear that the XS-40 board is history and being replaced by
the XS-50.
Does anyone know if Jan Gray's XSOC project will port to the XS-50
with t... XSOC2.0 [2 Articles]
guptaseen - Oct 13 2006
Hi all
i am new member here and was looking to learn and understand xr16 and
xsoc. i am unable to find XSOC2.0 code and documents. all i was able
to get was xsoc beta 0.93. is... async SRAM writes [2 Articles]
Jan Gray - Oct 22 2004
> I must have missed the part in the datasheet dealing with asymetric
> timing of read versus write. I have to get back into this as it may
> turn out that my syste... RE: xr16vx in JHDL is running on chip
Jan Gray - Jun 10 2001
Very well done, Mike! I can hardly wait to read more. One can floorplan in
JHDL, can't one?
For you JHDL folks, greetings, visit www.fpgacpu.org/xsoc/index.html ... Announcement: "Building a RISC System in an FPGA" magazine series, and XSOC/xr16 RISC SoC for XS40
Jan Gray, Gray Research LLC - Mar 15 2000
On behalf of Gray Research LLC, I am pleased to announce that the first of
three articles in the series "Building a RISC System in an FPGA" is now on
newsstands, in... Burched Spartan II and VHDL xsoc [8 Articles]
- May 22 2001
Hello,
It seems that at least two other people in thsi list are interested
in a port of the xsoc project to burched spartan II board using VHDL.
I was wond... Re: Execution unit in Verilog ?
Jan Gray - Nov 18 2004
If you google you shall find.
As well, the XR16 in the XSOC Kit ( http://fpgacpu.org/xsoc/ ) includes a
Verilog implementation.
As a schematic design came... FPGA-CPU on Burched Spartan2 Board [3 Articles]
Christian Plessl - Apr 30 2001
Hi!
Finally my mucht anticipated Burched Spartan2 evalboard
(www.burched.com.au) arrived.
I'm eager to start experimenting with FPGA CPUs. Did anybody try ... RE: Porting xr16 to XSV
Jan Gray - Dec 11 2000
I've been holding back my Virtex changes hoping to put together another
polished build of the whole XSOC kit. Alas I've been busy with other things
and this isn't h... XSOC/xr16 running on Virtex
Jan Gray - Oct 11 2000
This afternoon I resumed the Virtex port of XSOC/xr16/xr32 and am now
(finally) running XSOC/xr16 in my XESS XSV-300 prototyping board.
Today's work involved sev... simple kbbios/vbios for XSOC
Royce Liao - Jun 14 2001
I posted a *preliminary* version (as in incomplete) of
an XSOC-hosted keyboard/video BIOS. I've been working on this in
my spare time for the past month.
The... About software simulation of floating point with XSOC project [2 Articles]
Yi Zhang - Nov 5 2002
Hi, friends,
I am doing my master project about comparing the performance of XR-16 and Nios-16 on Altera Excalibur developing board. I use LU decomposion, writt... XSOC VGA controller [2 Articles]
- Nov 5 2000
I was thinking about modifying the VGA-controller on the XSOC chip,
to
enable a full blown alphanumeric display (fancy language for 'text
display'!) But I wonde... RE: Found link to Veriwell executable
Jan Gray - Aug 17 2000
Thank you, very helpful. Well, I was about to push this up to the web site:
"
Veriwell sightings
In the XSOC Getting Started Guide, I lament that I was unab... xsoc schematics in ISE WebPack
ts_oswald - Nov 30 2004
Hi -
I'm somewhat new to the fpga world and have been using the Xilinx ISE
WebPack version 6.2.03i with a Digilent D2FT board (Spartan XC2S300E).
To exp... xsoc-beta-092.zip dropped to www.fpgacpu.org/xsoc
Jan Gray, Gray Research LLC - Mar 22 2000
Welcome, new subscribers. We are now 17.
I have just uploaded beta 0.92 to the web site. This includes a fix for
issue #13, reported by Mike Butts, that the beta... Using XSOC
Jeffery, Robert - Feb 5 2002
Hi Jan.
I have been trawling your web site and found it most interesting. I am
interested in processor design and have found your site to be the most
useful, b... xr16 ISA reimplementation
Jan Gray - Apr 6 2001
> In this context I have a question to Jan Gray:
>
> Jan,
> do you consider the xr16 ISA as protected your license or just your
> HDL source code and documentat... about fpga-cpu (quarterly message) [4 Articles]
Jan Gray - Oct 2 2000
Welcome to October, 2000. This is the first instance of a quarterly message
about the proper care and feeding of the fpga-cpu list (and is not in
response to any sp... xr16vx in JHDL v1.0 is online
Mike Butts - Jun 30 2001
I've polished off the xr16vx microcontroller in JHDL, and
posted it, along with tools, tests and documentation:
http://www.easystreet.com/~mbutts/xr16vx_jhdl.htm... implementation of far branches in xr16
Sebastian Zuther - Sep 6 2001
I am trying to implement far branches in xr16asm (XSOC Project) and was
wondering if
anyone did this before. If so it would be nice if you post some lines of
code... RE: build problem
Jan Gray - May 26 2000
Hmm. I'm puzzled. My EDIF netlist differs from Leon's in surprising ways.
Here are some examples.
Jan's:
< (program "Aldec's EDIF Netlist Generator"
< (versi... Port to Spartan XL [2 Articles]
Mark Lefevere - May 30 2000
Hello all,
I have downloaded xsoc ver 093.
I like to port it to an XCS10XL using the schematic entry, has somebody
experience with?
Should I install foundation ... Xess board with XStend
Jamie R. Chinn - Mar 27 2000
I got the xsoc design to compile in Foundation Basic ver 2.1i. It took me a while to figure out how to reconfigure the outputs. Version 2.1i doesn't like the three... about fpga-cpu (recurring message) [5 Articles]
Jan Gray - Jan 3 2002
This is a recurring message on the proper care and feeding of the
fpga-cpu list.
1. Charter and Staying On Topic
"This list is for discussion of the design ... about fpga-cpu (recurring message)
Jan Gray - Sep 25 2001
This is a recurring message on the proper care and feeding of the
fpga-cpu list. Note that sections 2-4 are changed or new.
1. Charter and Staying On Topic
... RE: verilog vs Logiblox
Jan Gray - Aug 17 2000
> I'm in the process of designing my very own mpu and I noticed that if
> I create an adder / subtracter using LogiBlox (Xilinx F1.5 software)
> it takes up alot le... I'm using xsoc/tests/xr16
Mike Butts - Aug 31 2000
Hi, Jan! *Thank you* for writing the xr16 test. I'm putting it to
good use on my xr16vx design in simulation. I won't tell you
where it fails tonight ;-)
You ... RE: It's damaged?!?!?!
Jan Gray - Oct 18 2000
> I have downloaded Xsoc16 from www.fpgacpu.org,but Winzip tells me it has
> been damaged.Why?
All is well with xsoc-beta-093.zip, length 3340897 bytes, at least... Re: Constants in LCC-XR16 compiler
Jan Gray - Mar 31 2000
Jamie Chinn wrote:
<<<
A constant such as 0x8000 is by default treated as a four byte long. This
creates lots of errors. (Such as zexl and leal not found.) To wor...