Summary

Gene Breniman's 2008 VHDL tutorial covers practical techniques for combining clocked (synchronous) and sequential logic in VHDL to produce clear, synthesis-friendly RTL. The article highlights common pitfalls, coding patterns, and simulation checks that help ensure correct behavior on FPGAs and ASIC flows.

Key Takeaways

• Differentiate proper uses of clocked (registered) and combinational logic in VHDL code.
• Write synthesis-friendly VHDL patterns that avoid inferred latches and timing surprises.
• Apply simulation and testbench strategies to validate mixed synchronous/combinational designs.
• Recognize and avoid common pitfalls when mixing processes, signals, and variables across clock domains.

Who Should Read This

Intermediate FPGA and embedded engineers or firmware developers with basic VHDL experience who need practical guidance on mixing synchronous and combinational logic for robust RTL and FPGA designs.

TimelessIntermediate

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