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VHDL tutorial - Creating a hierarchical design
In earlier blog entries I introduced some of the basic VHDL concepts. First, developing a function ('VHDL tutorial') and later verifying and refining it ('VHDL tutorial - part 2 - Testbench' and 'VHDL...
posted by Gene Breniman on May 22 2008 under VHDL programming | Tutorials Comments (8) |
VHDL tutorial - combining clocked and sequential logic
In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this exampl...
posted by Gene Breniman on Mar 3 2008 under VHDL programming | Tutorials Comments (0) |
VHDL tutorial - part 2 - Testbench
In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE envir...
posted by Gene Breniman on Oct 30 2007 under VHDL programming | Tutorials Comments (2) |