In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE envir...
When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's stan...
With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of V...
In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC seque...
In earlier blog entries I introduced some of the basic VHDL concepts. First, developing a function ('VHDL tutorial') and later verifying and refining it ('VHDL tutorial - part 2 - Testbench' and 'VHDL...
In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream and stored in *.bit file. To compi...
Hello everybody, it’s nice to have an opportunity to write on embedded system and share experiments with readers. I recently started embedded systems in FPGA having luxury of reconfigurable ...