Hello, I'm trying to communicate with my RF module through UART interface.
However, I get many errors even with low load. I suspect that I have an issue
with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
http://glitovsky.com/blog/?p00
(I configured the connection as 8N1 at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with
MCLK MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */
UCSCTL3 &= ~SELREF_7;
UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK.
* Set SMCLK to use the DCO.
*/
UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
/* Initialize FLL. */
Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2;
UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
/* Enable interrupt for TBCCR0. */
TBCCTL0 = CCIE;
/* Number of ticks per millisecond. */
clock.aclk = 32768;
clock.ticks_per_interrupt = clock.aclk / 1000;
TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */
TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */
__bis_SR_register(GIE);
Thanks,
Mike
MSP430F5528 - Clock and UART
Started by ●February 17, 2015
Reply by ●February 17, 20152015-02-17
Why oh why are you bit banging this when the MSP430 has an extremely
simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
> Hello, I'm trying to communicate with my RF module through UART
> interface. However, I get many errors even with low load. I suspect
> that I have an issue with the way that I configure the clock or the UART.
> Basically, for the UART functionality I use
> http://glitovsky.com/blog/?p00
>
> (I configured the connection as 8N1 at 115200).
> The clock configuration below is used with MCLK = 25 MHz ( when I use
> it with MCLK MHz I cannot communicate with the UART module at all ) .
> P5SEL |= 0x0C;
>
> /* Select REF0 for FLL reference. */
>
> UCSCTL3 &= ~SELREF_7;
>
> UCSCTL3 |= SELREF_2;
> /* Set ACLK to use REF0CLK.
>
> * Set SMCLK to use the DCO.
>
> */
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>
> /* Initialize FLL. */
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
> XT2_Start(XT2DRIVE_0);
>
> UCSCTL4 &= ~SELA_7;
> UCSCTL4 |= SELA_2;
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
> /* Enable interrupt for TBCCR0. */
> TBCCTL0 = CCIE;
> /* Number of ticks per millisecond. */
> clock.aclk = 32768;
> clock.ticks_per_interrupt = clock.aclk / 1000;
> TBCCR0 = clock.ticks_per_interrupt;
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
> /* Enable interrupts. */
> __bis_SR_register(GIE);
> Thanks,
> Mike
>
simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
> Hello, I'm trying to communicate with my RF module through UART
> interface. However, I get many errors even with low load. I suspect
> that I have an issue with the way that I configure the clock or the UART.
> Basically, for the UART functionality I use
> http://glitovsky.com/blog/?p00
>
> (I configured the connection as 8N1 at 115200).
> The clock configuration below is used with MCLK = 25 MHz ( when I use
> it with MCLK MHz I cannot communicate with the UART module at all ) .
> P5SEL |= 0x0C;
>
> /* Select REF0 for FLL reference. */
>
> UCSCTL3 &= ~SELREF_7;
>
> UCSCTL3 |= SELREF_2;
> /* Set ACLK to use REF0CLK.
>
> * Set SMCLK to use the DCO.
>
> */
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>
> /* Initialize FLL. */
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
> XT2_Start(XT2DRIVE_0);
>
> UCSCTL4 &= ~SELA_7;
> UCSCTL4 |= SELA_2;
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
> /* Enable interrupt for TBCCR0. */
> TBCCTL0 = CCIE;
> /* Number of ticks per millisecond. */
> clock.aclk = 32768;
> clock.ticks_per_interrupt = clock.aclk / 1000;
> TBCCR0 = clock.ticks_per_interrupt;
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
> /* Enable interrupts. */
> __bis_SR_register(GIE);
> Thanks,
> Mike
>
Reply by ●February 17, 20152015-02-17
I believe you were looking for frightening not fightening".
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 3:07 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Why oh why are you bit banging this when the MSP430 has an extremely
simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
>
>
>
>
>
> Hello, I'm trying to communicate with my RF module through UART interface.
> However, I get many errors even with low load. I suspect that I have an issue
> with the way that I configure the clock or the UART.
>
>
>
>
> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>
>
> (I configured the connection as 8N1 at 115200).
>
>
>
>
>
> The clock configuration below is used with MCLK = 25 MHz ( when I use it with
> MCLK MHz I cannot communicate with the UART module at all ) .
>
>
>
>
> P5SEL |= 0x0C;
>
>
>
> /* Select REF0 for FLL reference. */
>
>
> UCSCTL3 &= ~SELREF_7;
>
>
> UCSCTL3 |= SELREF_2;
>
>
>
>
> /* Set ACLK to use REF0CLK.
>
>
> * Set SMCLK to use the DCO.
>
>
> */
>
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
>
>
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>
>
> /* Initialize FLL. */
>
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
>
>
>
>
> XT2_Start(XT2DRIVE_0);
>
>
>
>
> UCSCTL4 &= ~SELA_7;
>
>
> UCSCTL4 |= SELA_2;
>
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>
> /* Enable interrupt for TBCCR0. */
>
> TBCCTL0 = CCIE;
>
>
>
> /* Number of ticks per millisecond. */
>
> clock.aclk = 32768;
>
> clock.ticks_per_interrupt = clock.aclk / 1000;
>
> TBCCR0 = clock.ticks_per_interrupt;
>
>
>
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
>
>
>
> /* Enable interrupts. */
>
> __bis_SR_register(GIE);
>
>
>
>
>
>
> Thanks,
>
> Mike
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 3:07 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Why oh why are you bit banging this when the MSP430 has an extremely
simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
>
>
>
>
>
> Hello, I'm trying to communicate with my RF module through UART interface.
> However, I get many errors even with low load. I suspect that I have an issue
> with the way that I configure the clock or the UART.
>
>
>
>
> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>
>
> (I configured the connection as 8N1 at 115200).
>
>
>
>
>
> The clock configuration below is used with MCLK = 25 MHz ( when I use it with
> MCLK MHz I cannot communicate with the UART module at all ) .
>
>
>
>
> P5SEL |= 0x0C;
>
>
>
> /* Select REF0 for FLL reference. */
>
>
> UCSCTL3 &= ~SELREF_7;
>
>
> UCSCTL3 |= SELREF_2;
>
>
>
>
> /* Set ACLK to use REF0CLK.
>
>
> * Set SMCLK to use the DCO.
>
>
> */
>
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
>
>
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>
>
> /* Initialize FLL. */
>
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
>
>
>
>
> XT2_Start(XT2DRIVE_0);
>
>
>
>
> UCSCTL4 &= ~SELA_7;
>
>
> UCSCTL4 |= SELA_2;
>
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>
> /* Enable interrupt for TBCCR0. */
>
> TBCCTL0 = CCIE;
>
>
>
> /* Number of ticks per millisecond. */
>
> clock.aclk = 32768;
>
> clock.ticks_per_interrupt = clock.aclk / 1000;
>
> TBCCR0 = clock.ticks_per_interrupt;
>
>
>
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
>
>
>
> /* Enable interrupts. */
>
> __bis_SR_register(GIE);
>
>
>
>
>
>
> Thanks,
>
> Mike
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
Reply by ●February 17, 20152015-02-17
On 02/17/2015 09:51 AM, m...@yahoo.com [msp430] wrote:
> The clock configuration below is used with MCLK = 25 MHz ( when I use it
> with MCLK MHz I cannot communicate with the UART module at all ) .
How accurate is the clock frequency? Unless you are using a crystal, and
it looks like you aren't, the answer could be "not accurate enough".
--
David W. Schultz
http://home.earthlink.net/~david.schultz
Returned for Regrooving
Posted by: "David W. Schultz"
> The clock configuration below is used with MCLK = 25 MHz ( when I use it
> with MCLK MHz I cannot communicate with the UART module at all ) .
How accurate is the clock frequency? Unless you are using a crystal, and
it looks like you aren't, the answer could be "not accurate enough".
--
David W. Schultz
http://home.earthlink.net/~david.schultz
Returned for Regrooving
Posted by: "David W. Schultz"
Reply by ●February 17, 20152015-02-17
Well typing can be difficult when you only have limited use of your
hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com
[msp430] wrote:
> I believe you were looking for “frightening” not “fightening".
>
> From: "msp430@yahoogroups. com" > >
> Reply-To: "msp430@yahoogroups. com" > >
> Date: Tuesday, February 17, 2015 at 3:07 PM
> To: "msp430@yahoogroups. com" > >
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Why oh why are you bit banging this when the MSP430 has an extremely
> simple UART in hardware. Are interrupts that fightening?
>
> Al
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>>
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I suspect
>> that I have an issue with the way that I configure the clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I use
>> it with MCLK MHz I cannot communicate with the UART module at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com
[msp430] wrote:
> I believe you were looking for “frightening” not “fightening".
>
> From: "msp430@yahoogroups. com" > >
> Reply-To: "msp430@yahoogroups. com" > >
> Date: Tuesday, February 17, 2015 at 3:07 PM
> To: "msp430@yahoogroups. com" > >
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Why oh why are you bit banging this when the MSP430 has an extremely
> simple UART in hardware. Are interrupts that fightening?
>
> Al
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>>
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I suspect
>> that I have an issue with the way that I configure the clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I use
>> it with MCLK MHz I cannot communicate with the UART module at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
Reply by ●February 17, 20152015-02-17
Hi All,
First off, The first rule of software development is that the best code is
the one you didn't have to write ^^.
I agree with Al here, why aren't you using the build in UART tool in the
microprocessor. It is build to be used in this way, and the only reason
ever not to is if you have to use a certain chip and you have run out of
UART ports to use.
@Martin: Now you are just poking the bear aren't you.
Cheers,
Jake
On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au [msp430] <
m...> wrote:
> Why oh why are you bit banging this when the MSP430 has an extremely
> simple UART in hardware. Are interrupts that fightening?
>
> Al
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
> Hello, I'm trying to communicate with my RF module through UART
> interface. However, I get many errors even with low load. I suspect that
> I have an issue with the way that I configure the clock or the UART.
> Basically, for the UART functionality I use
> http://glitovsky.com/blog/?p00
>
> (I configured the connection as 8N1 at 115200).
> The clock configuration below is used with MCLK = 25 MHz ( when I use it
> with MCLK MHz I cannot communicate with the UART module at all ) .
> P5SEL |= 0x0C;
>
> /* Select REF0 for FLL reference. */
>
> UCSCTL3 &= ~SELREF_7;
>
> UCSCTL3 |= SELREF_2;
> /* Set ACLK to use REF0CLK.
>
> * Set SMCLK to use the DCO.
>
> */
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
> /* Initialize FLL. */
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
> XT2_Start(XT2DRIVE_0);
>
> UCSCTL4 &= ~SELA_7;
> UCSCTL4 |= SELA_2;
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
> /* Enable interrupt for TBCCR0. */
> TBCCTL0 = CCIE;
>
> /* Number of ticks per millisecond. */
> clock.aclk = 32768;
> clock.ticks_per_interrupt = clock.aclk / 1000;
> TBCCR0 = clock.ticks_per_interrupt;
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
> /* Enable interrupts. */
> __bis_SR_register(GIE);
> Thanks,
> Mike
>
>
--
Thomas J. Grajewski
First off, The first rule of software development is that the best code is
the one you didn't have to write ^^.
I agree with Al here, why aren't you using the build in UART tool in the
microprocessor. It is build to be used in this way, and the only reason
ever not to is if you have to use a certain chip and you have run out of
UART ports to use.
@Martin: Now you are just poking the bear aren't you.
Cheers,
Jake
On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au [msp430] <
m...> wrote:
> Why oh why are you bit banging this when the MSP430 has an extremely
> simple UART in hardware. Are interrupts that fightening?
>
> Al
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
> Hello, I'm trying to communicate with my RF module through UART
> interface. However, I get many errors even with low load. I suspect that
> I have an issue with the way that I configure the clock or the UART.
> Basically, for the UART functionality I use
> http://glitovsky.com/blog/?p00
>
> (I configured the connection as 8N1 at 115200).
> The clock configuration below is used with MCLK = 25 MHz ( when I use it
> with MCLK MHz I cannot communicate with the UART module at all ) .
> P5SEL |= 0x0C;
>
> /* Select REF0 for FLL reference. */
>
> UCSCTL3 &= ~SELREF_7;
>
> UCSCTL3 |= SELREF_2;
> /* Set ACLK to use REF0CLK.
>
> * Set SMCLK to use the DCO.
>
> */
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
> /* Initialize FLL. */
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
> XT2_Start(XT2DRIVE_0);
>
> UCSCTL4 &= ~SELA_7;
> UCSCTL4 |= SELA_2;
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
> /* Enable interrupt for TBCCR0. */
> TBCCTL0 = CCIE;
>
> /* Number of ticks per millisecond. */
> clock.aclk = 32768;
> clock.ticks_per_interrupt = clock.aclk / 1000;
> TBCCR0 = clock.ticks_per_interrupt;
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
> /* Enable interrupts. */
> __bis_SR_register(GIE);
> Thanks,
> Mike
>
>
--
Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
or get new hands ^^
On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au [msp430] <
m...> wrote:
> Well typing can be difficult when you only have limited use of your hands.
> I'll try to do better next time.
>
> Al
>
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
> wrote:
>
> I believe you were looking for “frightening” not “fightening".
>
> From: "msp430@yahoogroups. com" <
> m...>
> Reply-To: "msp430@yahoogroups. com" <
> m...>
> Date: Tuesday, February 17, 2015 at 3:07 PM
> To: "msp430@yahoogroups. com" <
> m...>
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Why oh why are you bit banging this when the MSP430 has an extremely
> simple UART in hardware. Are interrupts that fightening?
>
> Al
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
> Hello, I'm trying to communicate with my RF module through UART
> interface. However, I get many errors even with low load. I suspect that
> I have an issue with the way that I configure the clock or the UART.
> Basically, for the UART functionality I use
> http://glitovsky.com/blog/?p00
>
> (I configured the connection as 8N1 at 115200).
> The clock configuration below is used with MCLK = 25 MHz ( when I use it
> with MCLK MHz I cannot communicate with the UART module at all ) .
> P5SEL |= 0x0C;
>
> /* Select REF0 for FLL reference. */
>
> UCSCTL3 &= ~SELREF_7;
>
> UCSCTL3 |= SELREF_2;
> /* Set ACLK to use REF0CLK.
>
> * Set SMCLK to use the DCO.
>
> */
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
> /* Initialize FLL. */
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
> XT2_Start(XT2DRIVE_0);
>
> UCSCTL4 &= ~SELA_7;
> UCSCTL4 |= SELA_2;
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
> /* Enable interrupt for TBCCR0. */
> TBCCTL0 = CCIE;
>
> /* Number of ticks per millisecond. */
> clock.aclk = 32768;
> clock.ticks_per_interrupt = clock.aclk / 1000;
> TBCCR0 = clock.ticks_per_interrupt;
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
> /* Enable interrupts. */
> __bis_SR_register(GIE);
> Thanks,
> Mike
>
>
>
--
Thomas J. Grajewski
On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au [msp430] <
m...> wrote:
> Well typing can be difficult when you only have limited use of your hands.
> I'll try to do better next time.
>
> Al
>
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
> wrote:
>
> I believe you were looking for “frightening” not “fightening".
>
> From: "msp430@yahoogroups. com" <
> m...>
> Reply-To: "msp430@yahoogroups. com" <
> m...>
> Date: Tuesday, February 17, 2015 at 3:07 PM
> To: "msp430@yahoogroups. com" <
> m...>
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Why oh why are you bit banging this when the MSP430 has an extremely
> simple UART in hardware. Are interrupts that fightening?
>
> Al
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
> Hello, I'm trying to communicate with my RF module through UART
> interface. However, I get many errors even with low load. I suspect that
> I have an issue with the way that I configure the clock or the UART.
> Basically, for the UART functionality I use
> http://glitovsky.com/blog/?p00
>
> (I configured the connection as 8N1 at 115200).
> The clock configuration below is used with MCLK = 25 MHz ( when I use it
> with MCLK MHz I cannot communicate with the UART module at all ) .
> P5SEL |= 0x0C;
>
> /* Select REF0 for FLL reference. */
>
> UCSCTL3 &= ~SELREF_7;
>
> UCSCTL3 |= SELREF_2;
> /* Set ACLK to use REF0CLK.
>
> * Set SMCLK to use the DCO.
>
> */
>
> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>
> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
> /* Initialize FLL. */
> Init_FLL_Settle(mclk/1000L, mclk/32768);
>
> XT2_Start(XT2DRIVE_0);
>
> UCSCTL4 &= ~SELA_7;
> UCSCTL4 |= SELA_2;
> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
> /* Enable interrupt for TBCCR0. */
> TBCCTL0 = CCIE;
>
> /* Number of ticks per millisecond. */
> clock.aclk = 32768;
> clock.ticks_per_interrupt = clock.aclk / 1000;
> TBCCR0 = clock.ticks_per_interrupt;
>
> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>
> /* Enable interrupts. */
> __bis_SR_register(GIE);
> Thanks,
> Mike
>
>
>
--
Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
If he's setting up the FLL right he should be fine. I've never used
the
parts with FLL, but on other parts I can get reliable 460kb comms with
just the occasional tweak if temperature drifts too much, using a watch
crystal and the internal calibrated DCO data. The FLL is supposedly more
accurate than the calibrated DCO, but of course it depends on the
accuracy of the watch crystal to start with. I still think 115.2kb
should be easy, especially using the UART hardware and ints.
Al
On 18/02/2015 9:21 AM, 'David W. Schultz' d...@earthlink.net
[msp430] wrote:
> On 02/17/2015 09:51 AM, m...@yahoo.com [msp430] wrote:
>> The clock configuration below is used with MCLK = 25 MHz ( when I use it
>> with MCLK MHz I cannot communicate with the UART module at all ) .
> How accurate is the clock frequency? Unless you are using a crystal, and
> it looks like you aren't, the answer could be "not accurate enough".
>
Posted by: Onestone
parts with FLL, but on other parts I can get reliable 460kb comms with
just the occasional tweak if temperature drifts too much, using a watch
crystal and the internal calibrated DCO data. The FLL is supposedly more
accurate than the calibrated DCO, but of course it depends on the
accuracy of the watch crystal to start with. I still think 115.2kb
should be easy, especially using the UART hardware and ints.
Al
On 18/02/2015 9:21 AM, 'David W. Schultz' d...@earthlink.net
[msp430] wrote:
> On 02/17/2015 09:51 AM, m...@yahoo.com [msp430] wrote:
>> The clock configuration below is used with MCLK = 25 MHz ( when I use it
>> with MCLK MHz I cannot communicate with the UART module at all ) .
> How accurate is the clock frequency? Unless you are using a crystal, and
> it looks like you aren't, the answer could be "not accurate enough".
>
Posted by: Onestone
Reply by ●February 17, 20152015-02-17
Wrong, totally. the first rule of software development is that the best
code is the one that you personally know has been fully debugged, and
usually that is one that you wrote. If you trust others to write better
code than you then you are asking for a world of grief.
Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
> Hi All,
>
> First off, The first rule of software development is that the best
> code is the one you didn't have to write ^^.
>
> I agree with Al here, why aren't you using the build in UART tool in
> the microprocessor. It is build to be used in this way, and the only
> reason ever not to is if you have to use a certain chip and you have
> run out of UART ports to use.
>
> @Martin: Now you are just poking the bear aren't you.
>
> Cheers,
> Jake
>
> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
> [msp430] > > wrote:
>
> Why oh why are you bit banging this when the MSP430 has an
> extremely simple UART in hardware. Are interrupts that fightening?
>
> Al
>
> On 18/02/2015 2:21 AM, m...@yahoo.com
> [msp430] wrote:
>>
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I
>> suspect that I have an issue with the way that I configure the
>> clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I
>> use it with MCLK MHz I cannot communicate with the UART module
>> at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at
>> zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
> --
> Thomas J. Grajewski
code is the one that you personally know has been fully debugged, and
usually that is one that you wrote. If you trust others to write better
code than you then you are asking for a world of grief.
Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
> Hi All,
>
> First off, The first rule of software development is that the best
> code is the one you didn't have to write ^^.
>
> I agree with Al here, why aren't you using the build in UART tool in
> the microprocessor. It is build to be used in this way, and the only
> reason ever not to is if you have to use a certain chip and you have
> run out of UART ports to use.
>
> @Martin: Now you are just poking the bear aren't you.
>
> Cheers,
> Jake
>
> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
> [msp430] > > wrote:
>
> Why oh why are you bit banging this when the MSP430 has an
> extremely simple UART in hardware. Are interrupts that fightening?
>
> Al
>
> On 18/02/2015 2:21 AM, m...@yahoo.com
> [msp430] wrote:
>>
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I
>> suspect that I have an issue with the way that I configure the
>> clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I
>> use it with MCLK MHz I cannot communicate with the UART module
>> at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at
>> zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
> --
> Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
Spelling is important when bullying someone online.
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 4:02 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Well typing can be difficult when you only have limited use of your
hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
wrote:
>
>
>
> I believe you were looking for frightening not fightening".
>
>
>
>
> From: "msp430@yahoogroups. com"
>
> Reply-To: "msp430@yahoogroups. com"
>
> Date: Tuesday, February 17, 2015 at 3:07 PM
> To: "msp430@yahoogroups. com"
>
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
>
>
>
>
>
>
>
>
> Why oh why are you bit banging this when the MSP430 has an extremely simple
> UART in hardware. Are interrupts that fightening?
>
> Al
>
>
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
>
>>
>>
>>
>>
>>
>>
>> Hello, I'm trying to communicate with my RF module through UART interface.
>> However, I get many errors even with low load. I suspect that I have an issue
>> with the way that I configure the clock or the UART.
>>
>>
>>
>>
>> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>>
>>
>> (I configured the connection as 8N1 at 115200).
>>
>>
>>
>>
>>
>> The clock configuration below is used with MCLK = 25 MHz ( when I use it with
>> MCLK MHz I cannot communicate with the UART module at all ) .
>>
>>
>>
>>
>> P5SEL |= 0x0C;
>>
>>
>>
>> /* Select REF0 for FLL reference. */
>>
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>>
>> UCSCTL3 |= SELREF_2;
>>
>>
>>
>>
>> /* Set ACLK to use REF0CLK.
>>
>>
>> * Set SMCLK to use the DCO.
>>
>>
>> */
>>
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>>
>>
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>>
>> /* Initialize FLL. */
>>
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>>
>>
>>
>>
>> XT2_Start(XT2DRIVE_0);
>>
>>
>>
>>
>> UCSCTL4 &= ~SELA_7;
>>
>>
>> UCSCTL4 |= SELA_2;
>>
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>
>> /* Enable interrupt for TBCCR0. */
>>
>> TBCCTL0 = CCIE;
>>
>>
>>
>> /* Number of ticks per millisecond. */
>>
>> clock.aclk = 32768;
>>
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>>
>>
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>>
>>
>>
>> /* Enable interrupts. */
>>
>> __bis_SR_register(GIE);
>>
>>
>>
>>
>>
>>
>> Thanks,
>>
>> Mike
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
>
>
>
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 4:02 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Well typing can be difficult when you only have limited use of your
hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
wrote:
>
>
>
> I believe you were looking for frightening not fightening".
>
>
>
>
> From: "msp430@yahoogroups. com"
>
> Reply-To: "msp430@yahoogroups. com"
>
> Date: Tuesday, February 17, 2015 at 3:07 PM
> To: "msp430@yahoogroups. com"
>
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
>
>
>
>
>
>
>
>
> Why oh why are you bit banging this when the MSP430 has an extremely simple
> UART in hardware. Are interrupts that fightening?
>
> Al
>
>
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
>
>>
>>
>>
>>
>>
>>
>> Hello, I'm trying to communicate with my RF module through UART interface.
>> However, I get many errors even with low load. I suspect that I have an issue
>> with the way that I configure the clock or the UART.
>>
>>
>>
>>
>> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>>
>>
>> (I configured the connection as 8N1 at 115200).
>>
>>
>>
>>
>>
>> The clock configuration below is used with MCLK = 25 MHz ( when I use it with
>> MCLK MHz I cannot communicate with the UART module at all ) .
>>
>>
>>
>>
>> P5SEL |= 0x0C;
>>
>>
>>
>> /* Select REF0 for FLL reference. */
>>
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>>
>> UCSCTL3 |= SELREF_2;
>>
>>
>>
>>
>> /* Set ACLK to use REF0CLK.
>>
>>
>> * Set SMCLK to use the DCO.
>>
>>
>> */
>>
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>>
>>
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>>
>> /* Initialize FLL. */
>>
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>>
>>
>>
>>
>> XT2_Start(XT2DRIVE_0);
>>
>>
>>
>>
>> UCSCTL4 &= ~SELA_7;
>>
>>
>> UCSCTL4 |= SELA_2;
>>
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>
>> /* Enable interrupt for TBCCR0. */
>>
>> TBCCTL0 = CCIE;
>>
>>
>>
>> /* Number of ticks per millisecond. */
>>
>> clock.aclk = 32768;
>>
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>>
>>
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>>
>>
>>
>> /* Enable interrupts. */
>>
>> __bis_SR_register(GIE);
>>
>>
>>
>>
>>
>>
>> Thanks,
>>
>> Mike
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
>
>
>
