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Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is better: Verilog or VHDL?". But really I have not found a conclusive answer. why?, Each languages has advantages and disadvantages. However some designers think that Verilog has more advantages than VHDL... but again that depends of the point of view. Finally I want to recomend you some interesting links and reference that could help to decide what to use: 1) http://www.deepchip.com/items/snug00-07.html 2) There are some IEEE and ACM articles where a comparison is made -VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. Douglas J. Smith VeriBest Incorporated One Madison Industrial Estate.ACM. 1996 - Evaluation Criteria of HDLs : VHDL compared to Verilog, UDL/I & M Serge Maginot . 1993. ACM If you don't have access to the articles, I could send you a pdf version. ok.. bye. Friman S.C Jin Yan wrote: > Hi, everyone, > > I am new in this field. Could somebody kindly tell me > which one, VHDL or Verilog, is commonly used in > industry? Or which language is suitable to what kind > of application? > > I am choosing one language to do fpga programming and > wondering the pros and cons of these two languages in > industry and their usage. > > Thank you very much. > > Yan > > __________________________________________________ > > To post a message, send it to: > To unsubscribe, send a blank message to: > > ">http://docs.yahoo.com/info/terms/ -------------------- Friman Schez Casta. E-mail: Ph.D. Graduate Scholarship Holder o o o Computer Architecture Department o o o Technical University of Catalonia o o o C/Jordi Girona 1-3, Despatx C6-E208-7 U P C Tel. : (+34) 93-401 1655 Campus Nord,08034 Barcelona, Spain -------------------- |
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Re: VHDL and Verilog... the answer?
Started by ●February 25, 2003
Reply by ●February 25, 20032003-02-25
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Verilog or VHDL the first HDL's that I learned to design with were: CUPL, ABEL( altera's ), then Verilog. I fell in love with Verilog. Just before I learned verilog, I was using DesignBook ( consumed by Cadence ) graphicaly assembled HDL designs. Really poop code too. The real selling point of HDL for me was: I didn't have to deal with messy pages of schematics and I could organize my project and files the way I wanted to. I cant answer the initial question ' which is better ' But I can say this... I learned Verilog on the job mid-project, I learned Cadence Verilog XL, ModelSim, Xilinx alliance \ foundation. I 60 days I was profecient in the tools and steps of design flow & testing: I had also completed my portion of the design ' custom function UART instantiated into an OFDM modem design' All synchronous at 93.33mHz.. This meant constraints for timing were written by be in verilog (not generated by the tools ) Also models had been created in verilog, for the chip external fifo's interface, that were timing accurate and tested all IC timing violation and reported etc.. I cant say that verilog is better; but I can say that I learned all of that in 60 days. http://ca.geocities.com/artiedc --------------------------------- |
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Reply by ●February 26, 20032003-02-26
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> I cant say that verilog is better; but I can say that I learned all
of > that in 60 days. Note that a lot of people (especially software people) don't understand that you have to learn digital hardware design first before you can learn the HDL (whether that's Verilog, VHDL, or something else). If you don't already know how to design digital hardware, the HDL won't do you much good. The HDL synthesizer isn't magic; it can't do a good job of translating a complex high-level behavioral design into hardware for you. It's quite plausible for someone who already knows.digital design to become fairly fluent in an HDL in 60 days. But if you don't already know digital design, it will take much longer. |
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Reply by ●February 26, 20032003-02-26
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Great point Eric Smith <> wrote:> I cant say that verilog is better; but I can say that I learned all of > that in 60 days. Note that a lot of people (especially software people) don't understand that you have to learn digital hardware design first before you can learn the HDL (whether that's Verilog, VHDL, or something else). If you don't already know how to design digital hardware, the HDL won't do you much good. The HDL synthesizer isn't magic; it can't do a good job of translating a complex high-level behavioral design into hardware for you. It's quite plausible for someone who already knows.digital design to become fairly fluent in an HDL in 60 days. But if you don't already know digital design, it will take much longer. To post a message, send it to: To unsubscribe, send a blank message to: ">http://docs.yahoo.com/info/terms/ --------------------------------- |
