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I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year project titled "Writing an instruction stream generator for a DUV". Currently, I am having problems finding a DUV. Could anyone tell me where I could find a LEON Verilog simulation? Much appreciated, Howling Mad Wilger. |
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LEON Verilog simulation
Started by ●November 1, 2002
Reply by ●November 1, 20022002-11-01
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Hi Howling. As far as I am aware there is only a VHDL model for the Leon design. Check out the following sites. http://www.gaisler.com/ http://www.leox.org/ Cheers. Robert. -----Original Message----- From: howlingmadwilger [mailto:] Sent: 01 November 2002 11:52 To: Subject: [fpga-cpu] LEON Verilog simulation I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year project titled "Writing an instruction stream generator for a DUV". Currently, I am having problems finding a DUV. Could anyone tell me where I could find a LEON Verilog simulation? Much appreciated, Howling Mad Wilger. To post a message, send it to: To unsubscribe, send a blank message to: ">http://docs.yahoo.com/info/terms/ |
Reply by ●November 1, 20022002-11-01
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1. Please define DUV for us. 2. There is a *VHDL* model for LEON SPARC at http://www.gaisler.com/main.html. 3. What does a "DUV" have to do with LEON SPARC? Jan Gray, Gray Research LLC |
