Debugging by bsing SW interrupts instead of HW interrupts

My problem is to test my driver software ,but the asic chip  is not
ready yet.I can simulate the registers of the asic easyly,but the
HW interrupts which will be generated by asic chip is necessary to
test my interrupt handler and interrupt driven SW.
For X86 processor I know that also SW interrupt generation is possible
but how?
How should I write interrupt handler for a SW interrupt?
Does anybody have an example or link about these?

istakoz2000@yahoo.com wrote:
> My problem is to test my driver software ,but the asic chip  is not
> ready yet.I can simulate the registers of the asic easyly,but the
> HW interrupts which will be generated by asic chip is necessary to
> test my interrupt handler and interrupt driven SW.

Just make a little interrupt generator, could be just a pushbutton, a 
Schmitt inverter, a resistor and a cap (depending on how your interrupts 
work), and tag that onto the appropriate interrupt signal. Push the 
button, and step your way through the bugs!

Paul Burke

In X86 32-bit assembler, you can test your interrupt routine by:

  PUSHFD
  CALL    FAR isr_address

or

  PUSHFD
  PUSH    CS
  CALL    NEAR isr_address

But because your hardware isn't actually signalliung an interrupt,
register reads in the ISR may not give what you'd expect, so this will
really just check the prolog/epilog code of your IST handler.

It would be preferable to actually trigger the hardware interrupt
proper. If you need to pull a line up or down, just have a 10k resistor
running to Vcc or ground and touch it to the relevant line. Presuming
this is practicable of course.

S/W ints are no replacement for H/W ints, but are generally used to
supply a different functionality.

Regards,
Alfie.

Externally triggering of interrupt pin  seems to be practical .
I will try.Thank you.

Husnu Ayduk

AlfieNoakes@blueyonder.co.uk yazdi:
> In X86 32-bit assembler, you can test your interrupt routine by:
>
>   PUSHFD
>   CALL    FAR isr_address
>
> or
>
>   PUSHFD
>   PUSH    CS
>   CALL    NEAR isr_address
>
> But because your hardware isn't actually signalliung an interrupt,
> register reads in the ISR may not give what you'd expect, so this will
> really just check the prolog/epilog code of your IST handler.
>
> It would be preferable to actually trigger the hardware interrupt
> proper. If you need to pull a line up or down, just have a 10k resistor
> running to Vcc or ground and touch it to the relevant line. Presuming
> this is practicable of course.
>
> S/W ints are no replacement for H/W ints, but are generally used to
> supply a different functionality.
> 
> Regards,
> Alfie.

<istakoz2000@yahoo.com> wrote in message 
news:1124437784.844440.312570@g43g2000cwa.googlegroups.com...
> Externally triggering of interrupt pin  seems to be practical .
> I will try.Thank you.

Be a bit careful - using a switch or some other manual means will result in 
bounce, and you're likely to see multiple interrupts. You might consider 
using some external logic to ensure that your IRQ pin only sees a single 
transition. You could for instance use a 555 to generate a regular LF IRQ, 
and use a switch to enable/disable the 555. Just a thought.

Steve
http://www.fivetrees.com