LPC2000

Hi all.


Could anyone explane me about ARM timing.
I have a LPC2294 and external RAM (32, 0ws).

Source:
	while(1)
	{
		volatile uint32_t* extRam = (uint32_t*)0x80000000;
		register uint32_t zero = 0;
		register uint32_t one = 0xffffffff;

		extRam[0] = zero;
		extRam[0] = one;
		extRam[0] = zero;
		extRam[0] = one;
........................
........................
		extRam[0] = zero;
		extRam[0] = one;
	}
}

 497              		mov	r3, #-2147483648
 498 0348 FEFFFFEB 		mov	r1, #0
 499 034c 0231A0E3 		mvn	r2, #0
 500 0350 0010A0E3 	.L42:
 501 0354 0020E0E3 	.LBE11:

 507              		str	r1, [r3, #0]
 508              		.loc 1 337 0
 509 0358 001083E5 		str	r2, [r3, #0]
 510              		.loc 1 338 0
 511 035c 002083E5 		str	r1, [r3, #0]
 512              		.loc 1 339 0
 513 0360 001083E5 		str	r2, [r3, #0]
 514              		.loc 1 340 0
 515 0364 002083E5 		str	r1, [r3, #0]
 516              		.loc 1 341 0
 517 0368 001083E5 		str	r2, [r3, #0]
 518              		.loc 1 342 0
 519 036c 002083E5 		str	r1, [r3, #0]
 520              		.loc 1 343 0
........................
........................


So i'ts software only set 4 bytes in external memory to from 0x000000
to 0xffffff.
If I understand right, str command take a one clock cycle, and writing
to extRam another cycle.
But when I check by oscilloscope, I have only 10mZh at data bus. I
check BLS signal. I'ts 1 with two cycles and 0 (writing) one cycle.

Why it's take 3 cycles?

Try this question in comp.sys.arm, maybe you'll have better luck.

Artem wrote:
> But when I check by oscilloscope, I have only 10mZh at data bus. I
> check BLS signal. I'ts 1 with two cycles and 0 (writing) one cycle.

The LPC external memory interface is rather slow, compared to the CPU.

Examine your LPC user manual, look for the BCFG0 .. BCFG3 registers.

There's may be at least one wait-state before the ARM will even start
wiggling a CS line. (IDCY field)

Then the actual access cycle takes at least 3 clocks (WST1 or WST2
field)

The reset defaults for these registers are all set to the longest
delay possible.

But even when setting these registers to the lowest values,
you cannot go below 3 clocks per access.

Anyway, you did start up the PLL, did you? If not your ARM
will run with the XTAL clock only.

Greetings,
  Olav

Artem,

the benefits of LPC2000 device are in fast execution from internal
memory as all higher end devices. External memory will always be slower
because you need to go through bus bridges inside the device, needing
to be synchronized and slowing down the access. This is why internal
execution will be faster ( in the case of the LPC2000 also from Flash)
than external execution even if your memory is 0 WS.

An Schwob

O=2E W=F6lfelschneider wrote:
> Artem wrote:
> > But when I check by oscilloscope, I have only 10mZh at data bus. I
> > check BLS signal. I'ts 1 with two cycles and 0 (writing) one cycle.
>
> The LPC external memory interface is rather slow, compared to the
CPU.
>
> Examine your LPC user manual, look for the BCFG0 .. BCFG3 registers.
>
> There's may be at least one wait-state before the ARM will even start
> wiggling a CS line. (IDCY field)
>
> Then the actual access cycle takes at least 3 clocks (WST1 or WST2
> field)
>
> The reset defaults for these registers are all set to the longest
> delay possible.
>
> But even when setting these registers to the lowest values,
> you cannot go below 3 clocks per access.
>
> Anyway, you did start up the PLL, did you? If not your ARM
> will run with the XTAL clock only.
>=20
> Greetings,
>   Olav