H8/3867 Synchronous Uart False Clocks...

Does anybody know how to reset an H8 /3867 synchronous
uart when it is part way through receiving a data byte?
I have tried toggling the RE bit, apparently to no avail.

I believe that noise may be causing a false clock so that
the uart clocks in the first bit. Some period later, the
real data is sent and the uart will raise RDRF after 7 bits
have been received. One protection against this would be
to reset the uart when expecting data. There is no obvious
way that I can see to do this, except by toggling RE, but
this appears not to work. Does anyone know if toggling
RE does indeed reset the receiver? I guess there must be
some kind of FSA which returns to its initial state after
8 clocks. Is there any other way to persuade it to reset?

Many thanks,

Paul

On Tuesday, in article
     <40e15232$0$22499$7b0f0fd3@mistral.news.newnet.co.uk>
     phackney@hanoverdisplays.com "Paul Hackney" wrote:

Plenty of experience with asynchronous on H8 (see sig)

>Does anybody know how to reset an H8 /3867 synchronous
>uart when it is part way through receiving a data byte?
>I have tried toggling the RE bit, apparently to no avail.

Why do it that way?

How can you be sure that the time between toggling off and on again
will ensure that no more data bits will be received?

You do of course do at least two read cycles to clear all the receive
buffers as well.

>I believe that noise may be causing a false clock so that
>the uart clocks in the first bit. Some period later, the

Alternativeley you reenabled BEFORE the last data bits have passed.

>real data is sent and the uart will raise RDRF after 7 bits
>have been received. One protection against this would be

Which is what synchronous mode is supposed to do, raise RDRF after
8 bits of data.

>to reset the uart when expecting data. There is no obvious
>way that I can see to do this, except by toggling RE, but
>this appears not to work. Does anyone know if toggling
>RE does indeed reset the receiver? I guess there must be

Normally RE just enables/disables the receiver, it does NOT reset
the receiver.

Even in asynchronous mode when enabling the receiver it is always
advisable to discard the first at least two bytes received as there
may have been data on the receive line which will give scrambled results.

>some kind of FSA which returns to its initial state after
>8 clocks. Is there any other way to persuade it to reset?

Why do you need to reset the receiver at all?

The simpler method is discard known garbage data, as you must be using
some form of synchronisation process with the data.

Monitor the I/O pin for a known idle period before enabling the
receiver. Once you have valid bytes being received just leave the
receiver enabled.

-- 
Paul Carpenter		| paul@pcserv.demon.co.uk
<http://www.pcserv.demon.co.uk/>        Main Site
<http://www.gnuh8.org.uk/>              GNU H8 & mailing list info.
<http://www.badweb.org.uk/>             For those web sites you hate.

Paul,

Thanks for your reply. You ask a couple of questions which
I shall attempt to answer.

Why toggle RE? An attempt to reset the uart, is the short answer;
normally the uart is permanently enabled.

Why do I need to reset the receiver? Again, normally I wouldn't, but
if a glitch on the line causes a false clock I need to reset the internal
state to its initial state when I am expecting real data, otherwise the
data will be corrupt.

You have given me an idea though ;-)

Paul.


"Paul Carpenter" <paul$@pcserv.demon.co.uk> wrote in message
news:20040629.2113.301082snz@pcserv.demon.co.uk...
> On Tuesday, in article
>      <40e15232$0$22499$7b0f0fd3@mistral.news.newnet.co.uk>
>      phackney@hanoverdisplays.com "Paul Hackney" wrote:
>
> Plenty of experience with asynchronous on H8 (see sig)
>
> >Does anybody know how to reset an H8 /3867 synchronous
> >uart when it is part way through receiving a data byte?
> >I have tried toggling the RE bit, apparently to no avail.
>
> Why do it that way?
>
> How can you be sure that the time between toggling off and on again
> will ensure that no more data bits will be received?
>
> You do of course do at least two read cycles to clear all the receive
> buffers as well.
>
> >I believe that noise may be causing a false clock so that
> >the uart clocks in the first bit. Some period later, the
>
> Alternativeley you reenabled BEFORE the last data bits have passed.
>
> >real data is sent and the uart will raise RDRF after 7 bits
> >have been received. One protection against this would be
>
> Which is what synchronous mode is supposed to do, raise RDRF after
> 8 bits of data.
>
> >to reset the uart when expecting data. There is no obvious
> >way that I can see to do this, except by toggling RE, but
> >this appears not to work. Does anyone know if toggling
> >RE does indeed reset the receiver? I guess there must be
>
> Normally RE just enables/disables the receiver, it does NOT reset
> the receiver.
>
> Even in asynchronous mode when enabling the receiver it is always
> advisable to discard the first at least two bytes received as there
> may have been data on the receive line which will give scrambled results.
>
> >some kind of FSA which returns to its initial state after
> >8 clocks. Is there any other way to persuade it to reset?
>
> Why do you need to reset the receiver at all?
>
> The simpler method is discard known garbage data, as you must be using
> some form of synchronisation process with the data.
>
> Monitor the I/O pin for a known idle period before enabling the
> receiver. Once you have valid bytes being received just leave the
> receiver enabled.
>
> -- 
> Paul Carpenter | paul@pcserv.demon.co.uk
> <http://www.pcserv.demon.co.uk/>        Main Site
> <http://www.gnuh8.org.uk/>              GNU H8 & mailing list info.
> <http://www.badweb.org.uk/>             For those web sites you hate.
>