Can distributed RAM on Xilinx FPGA be modified by onchip processor at run time and can output of the same connected to shift register in CLB.

Hi, 

I am newbie in FPGA field. I am trying to implement look up table based
logic on Xilinx FPGA. I want to implement the look up table in  distributed
RAM and to connect the output of RAM to implement the logic in LUT. And to
get reconfigurability modify the RAM content at run time by soft core
processor on the same chip. Can anybody let me know if it is feasible or
not.

Thanks,
Indra

On Jul 14, 7:58=A0am, "iwgauba" <iwga...@yahoo.com> wrote:

> I am newbie in FPGA field. I am trying to implement look up table based
> logic on Xilinx FPGA. I want to implement the look up table in =A0distrib=
uted
> RAM and to connect the output of RAM to implement the logic in LUT. And t=
o
> get reconfigurability modify the RAM content at run time by soft core
> processor on the same chip. Can anybody let me know if it is feasible or
> not.

It is possible if you have sufficient resources in the FPGA for the
size ram you want and learn to interface this to the soft core
processor.

Can you not use one of the block ram primitives instead?  There tends
to be a lot more of that available.