Beware of Analog Switch Leakage Current

I’ve written about leakage current of CMOS circuitry several times previously, but it’s always been as a warning tossed aside, something to scare inexperienced youngsters, like the boogeyman or the chupacabra. Today I want to show you a specific example.

Let’s say I want to make a switchable reference that takes a 1.25V reference voltage and either buffers it or multiplies it by a gain of 2. I have three ideas of circuits that will do this:

In all cases, I have a CMOS op-amp, and resistors R1 = R2 = 10KΩ. In designs A and B, I have a Nexperia 74LVC1G66 single-pole single-throw (SPST) analog switch for S1; in design C I have a Nexperia 74LVC1G53 single-pole double-throw (SPDT) analog multiplexer.

I want this design to work over a temperature range of -40 to +85°C. Which of the designs will give me the smallest worst-case error in the output Vo?

(Before reading on, take the quiz!)

Op Amp Leakage Current

Since I mentioned leakage current in the first paragraph, it’s worth understanding what the leakage current specs are for our CMOS components.

CMOS op-amps usually have input bias current specs (the leakage into or out of the input pins) of picoamps at room temperature; you rarely find specs even at elevated temperature beyond one or two nanoamps.

Here are a few examples:

• Microchip MCP6486: 200 pA typical at 125°C
• ON Semi LMV321: 1 nA typical at high end of temperature range
• STMicro TS272: 300 pA max at 125°C
• Analog Devices AD8541: 500 pA max at 125°C
• Texas Instruments TLC272: 2000 pA max at 85°C (220 pA typical)

CMOS op-amps have such a low input bias current thanks to the fact that the inputs are MOSFET gates in differential pairs; the gates have this nice silicon dioxide insulating layer — remember, MOSFET = Metal Oxide Semiconductor Field Effect Transistor — so they are inherently very high impedance. Here’s the equivalent schematic for the TLC272:

In fact, the input bias current specs are probably dominated by electrostatic discharge protection circuitry characteristics, rather than the gate leakage current itself. For the TLC272, this is not shown in the equivalent schematic, but is mentioned fairly clearly in the datasheet text (my emphasis):

The TLC272 and TLC277 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode.

The input ESD protection probably looks something like this on each of the IN- and IN+ pins:

Maybe there’s two pairs of diodes, each pair connecting a circuit node to both Vdd and Vss. Maybe there’s only the inner pair, closer to the gate; maybe there’s only the outer pair; maybe the resistor/diodes are one big monolithic thing that is approximated by the circuit I showed here. I don’t know, I’m not a chip designer, but the idea of ESD diodes connected to the supply pins, that are normally reverse-biased, is so common that it should be second nature for any engineer to imagine that they’re there on every input and output, protecting us from damaging that fragile oxide layer when we reach out and touch some circuit board carelessly on a dry day. It’s no longer the old days of the Wild West, when men were men and CMOS ICs would wither and die if you got too close with even the smallest amount of electric charge. Actually, I no longer know which chips were most susceptible to ESD; I seem to remember the old CD4000 logic chips were notorious for ESD damage, but even fifty years ago, in the 1975 RCA COS/MOS databook, ESD protection is mentioned very clearly:

The 1979 RCA COS/MOS databook describes this structure a little more in detail as a “distributed resistor-diode network”:

In any case: ESD protection design is something best left to the chip design experts; as a circuit designer, all you really need to know is that there are effectively diodes from the input node to both Vdd and Vss, and unless you pull the input node outside the power supply range, these diodes will never be forward-biased and the leakage current is minimal. Picoamps for op-amp inputs, maybe a nanoamp or two if you heat them to their upper temperature limit.

Analog switch leakage current

Analog switches also have leakage current. The typical CD4066-equivalent switch has five signal MOSFETs and some logic, and looks like this:

Diagram annotated from Fairchild CD4066BC datasheet

Transistors Q1 (N-channel) and Q2 (P-channel) are the main pass transistors that form a transmission gate, which connects the two input terminals together when the control signal is enabled, turning Q1 and Q2 on; they disconnect the inputs when the control signal is disabled. Transistors Q3 (N-channel) and Q4 (P-channel) form an auxiliary transmission gate, that connects Q1’s body (node “B”) to the two input terminals when the control signal is enabled; when the control signal is disabled, transistor Q5 (N-channel) turns on and connects Q1’s body to the negative power supply node Vss. This funny business with transistors Q3, Q4, and Q5 helps reduce the on-resistance of transistor Q1, lowering the effective switch on-resistance. (The mechanism here is reducing the source-body voltage, which reduces the gate threshold; for more information, see the body effect) If you don’t want the funny business, get a CD4016-equivalent switch with just the two transistors (Q1 and Q2) and live with the increased on-resistance.

The analog switch I mentioned in the beginning is a Nexperia 74LVC1G66, which has the same circuit idea, only this time Q1, Q3, and Q5 are P-channel and Q1’s body (node B) is pulled up to the positive rail when the switch input terminals are disconnected. Same idea though: one primary transmission gate formed by an N- and a P-channel MOSFET connected together, and some other transistors to reduce Q1’s on-resistance by messing with its body diode voltage.

Diagram annotated from Nexperia 74LVC1G66 datasheet

The drain-body and source-body junctions of Q1 and Q2 create a path for leakage current to flow. The leakage specs for the analog switch terminals are given in the datasheet:

• ±0.2 µA off-state leakage current at 5.5V supply voltage, over the -40 to +85°C temperature range, with one input at Vcc and the other at GND, which applies maximum voltage across the switch
• ±1.0 µA on-state leakage current at 5.5V supply voltage, over the -40 to +85°C temperature range

They even give you a circuit diagram showing how they measure leakage current! The leakage current can depend on a lot of things: temperature, voltage across the switch, phase of the moon, etc., but since we don’t have any information about leakage current vs. switch voltage, all we can assume are those worst-case specs.

There’s also a spec for on-resistance; for 3.3V supply, the worst-case (“peak”) on resistance over the voltage range is typically 7.8 Ω and has an absolute maximum of 20 Ω.

The SPDT analog switch of the 74LVC1G53 has the same specs: ±0.2 µA off-state leakage current, ±1.0 µA on-state leakage current, 7.8 Ω typical 20 Ω maximum on resistance.

Now we have enough information to analyze the three circuits I posted at the beginning.

Circuit Analysis of Leakage Current

Here are those three circuits, redrawn slightly to show nonzero switch resistance Ron and leakage currents into the switch terminals. (Reminder: R1 = R2 = 10KΩ)

Note that I haven’t drawn in the op amp input bias currents. This is because even the 2 nA max bias current of the TLC272 will appear across at most 10 KΩ, for an error of 20 µV, much smaller than the other errors we are about to calculate.

Also note for the SPST switch in circuits A and B, the two on-state leakage currents add up worst-case to the single on-state leakage current spec of 1.0 µA; you don’t get twice the spec with max leakage current from both sides at once. (To see why, look at the test circuit in Figure 5 from the 74LVC1G66 datasheet, which effectively measures the sum of both)

I’m going to neglect offset voltage of these op amps, which has the same effect in all three configurations.

Circuit A

When switch S1 is off:

• Off-state leakage current ILoff ≤ 0.2 µA flows through the top end of the switch, R2, and R1, increasing the output voltage Vo by R1 × ILoff = 2mV worst-case. (The op amp forces the low end of R1 to equal 1.25 V.)

Net error: 2mV max from leakage current ILoff × R1; other sources insignificant.

When switch S1 is on:

• Nominal load current through R1 and R2 is 125 µA.
• Effect of Ron (max = 20 Ω) is an error of 125 µA × 20 Ω = 2.5 mV
• On-state leakage current ILon ≤ 1.0 µA is shunted to ground via Ron = at most 20 µV.

Net error: 2.5mV max from Ron × load current through R1 and R2; other sources insignificant.

Circuit B

When switch S1 is off:

• Off-state leakage current ILoff ≤ 0.2 µA flows through the top end of the switch and R1, increasing the output voltage Vo by R1 × ILoff = 2mV worst-case. (The op amp forces the low end of R1 to equal 1.25 V.)
• Off-state leakage current ILoff also can flow through R2, causing a nonzero voltage, but since the switch is off, this doesn’t impact the behavior of the rest of the circuit.

Net error: 2mV max from leakage current ILoff × R1; other sources insignificant.

When switch S1 is on:

• Nominal load current through R1 and R2 is 125 µA.
• Effect of Ron (max = 20 Ω) is an error of 125 µA × 20 Ω = 2.5 mV
• On-state leakage current ILon ≤ 1.0 µA flows through R1, for an increase in output of 10 mV max. (Op amp maintains voltage at the upper end of the switch, so there is no change in current through R2.)

Net error: 12.5mV max

• 2.5mV from Ron × load current through R1 and R2
• 10mV from leakage current ILon × R1.

Circuit C

When switch S1 connects the op amp negative input terminal to the op amp output (output = 1.25 V nominal):

• On-state leakage through the top current source flows through the low-impedance op amp output, with no effect on output voltage. (Well, the on-state leakage current could be on the other side of the switch and flow through Ron before reaching the op amp output, for a worst-case error of Ron × ILon = 20 Ω × 1 µA = 20 µV.)
• Off-state leakage through the bottom current source gets split between R1 and R2, but this doesn’t matter because R1 and R2 are just a load on the output, and changes in current don’t affect the output voltage.

Net error: 20 µV max from leakage current ILon × Ron.

When switch S1 connects the op amp negative input terminal to the voltage divider midpoint (output = 2.50 V nominal):

• Off-state leakage through the top current source flows through the low-impedance op amp output, with no effect on output voltage.
• On-state leakage through the bottom current source flows through either R1, if current is as shown, or through R1 + Rout if leakage current is on the other side of the switch. (Op amp maintains voltage across R2, so there is no change in current through R2.) Worst-case error is 1.0 µA × (10 kΩ + 20 Ω) ≈ 10 mV.

Net error: 10 mV max

• 10 mV from leakage current ILon × R1.

Summary

Here’s a summary of those worst-case output voltage errors:

Again, for this circuit and these analog switches,

• \( |I_{Loff}| \le \) 0.2 µA in the −40 to +85°C range
• \( |I_{Lon}| \le \) 1.0 µA in the −40 to +85°C range
• \( |R_{on}| \le \) 20 Ω

So Circuit A wins, with Circuits B and C having larger worst-case errors because of the effect of on-state leakage current — at least with this choice of component values.

Improvements

We could improve the situation in three ways:

• Accept a lower maximum temperature range. Leakage current roughly doubles every 10°C in silicon process technologies. For some reason the analog switch manufacturers don’t include characterization data for leakage currents, but they do for op amps; here’s the appropriate graph for the TLC272:

  

  With these circuits, the only error source that isn’t driven by leakage current is for the gain of 2 with circuit A, which depends on the switch on-resistance.

• Use lower-value feedback resistors. This would decrease the voltage error due to leakage currents. Circuit C’s voltage error is unrelated to current through \( R_1 + R_2 \); the only contribution of error from on-resistance Ron is the product of leakage current and Ron. Circuits A and B don’t benefit much from reducing the feedback resistors, since the increased current flows through the switch, and this increases errors due to Ron.

  If we made R1 = R2 = 1KΩ then the maximum error in Circuit C would drop to 1 mV.

• Use a better analog switch, with lower specified leakage currents. I mentioned improved analog switches in 10 Circuit Components You Should Know, for example the ON Semi FSA4157 and Vishay DG4157 for a small and relatively inexpensive 2:1 multiplexer with better on-resistance specs (FSA4157: 4.3 Ω for Vcc = 2.7 V, DG4157: 3 Ω for Vcc = 2.7 V) and better leakage specs (both parts specify 40 nA max on-state leakage, 20 nA max off-state leakage).

Credit for Circuit C goes to Analog Devices, which has a few articles on analog switches that discuss this topology to avoid voltage error due to switch on-resistance.

Also, note that there is really no reason to use Circuit B; in general, if you have a choice of where to place a switch among components in series, choose the location with the lowest source impedance so that errors due to on-state leakage currents are minimized.

Wrapup

We looked at a couple of related issues today:

• the cause of leakage currents in CMOS op amps and analog switches
• some of the characteristics of analog switches
• the effect of leakage current in the three adjustable-gain circuits

Leakage current in analog switches is something that you need to be aware of: it’s significant at higher temperatures and will cause circuit errors more often than you might think.

Hope you found this useful!

References

• Walt Kester, Analog Devices Tutorial MT-088: Analog Switches and Multiplexers Basics, October 2008.
• Jeff Watson and Gustavo Castro, High-Temperature Electronics Pose Design and Reliability Challenges, Analog Dialogue, April 2012.
• Usama Munir and David Canny, Maxim Integrated Products Application Note 5299: Selecting the Right CMOS Analog Switch, January 2013.
• Renesas AN522: Recommended Test Procedures for Analog Switches, October 2002.
• Siliconix, Analog Switches and their Applications, 1976.
• Barry Harvey, On Building Physically Accurate Analog Switch Macromodels, Analog Dialogue, January 2020.

© 2025 Jason M. Sachs, all rights reserved.