We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards

I'm trying to simulate a design and I need the Xilinx block ram instances and CLKDLL to simulate. But they aren't included in ...

I'm trying to simulate a design and I need the Xilinx block ram instances and CLKDLL to simulate. But they aren't included in ModelSim by default. I tried to add the libraries from the Xilinx directory, but the OK button in the ModelSim add library dialog is greyed out. Do

Hi folks, I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 and Xilinx ISE. Can someone tell me what...

Hi folks, I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 and Xilinx ISE. Can someone tell me what is the method to link my cpu design to an internal ROM. By internal I mean a ROM made inside the Xilinx chip. I can use coregen to create the componen

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a...

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a microcontroller(ATMEGA8535) and the microcontroller is eventually connected to Xilinx Virtex4 (ML401).It is actually road traffic light implementation for Emergency Vehicle Preemption System. My friend told me that I could do this by implementing a Microbl...

I searching for any info on how to decode the "raw data" in the bit file which is created from the Xilinx Foundation software...

I searching for any info on how to decode the "raw data" in the bit file which is created from the Xilinx Foundation software package. I have successfully found info on the header fields but I can't find anything on the "raw data" section which is used to progr

Hi, all. I build an Apple-I clone on the Spartran3 starter kit, and placed it on my web site. http://www.ip-arch.jp/indexe.html The all...

Hi, all. I build an Apple-I clone on the Spartran3 starter kit, and placed it on my web site. http://www.ip-arch.jp/indexe.html The all logics are written with SFL, but you can convert to verilog with my tool (sfl2vl) on the above site. The archive includes logic files under SFL folder Xilinx UCF and BMM and MEM files and BIT file under Xilinx folder and readme.txt (attached bel...

Not really an FPGA-CPU related post but this might be worth checking out. Xilinx has a CPLD development board (XC2-XL) for $50...

Not really an FPGA-CPU related post but this might be worth checking out. Xilinx has a CPLD development board (XC2-XL) for $50 that has the XC9500XL and CoolRunner II (256 macrocell) CPLDs plus prototyping area. Given the included access to a bunch of reference

I have recently noticed that Xilinx has changed the WebPACK download page: it now requires USER \ PWD login. I am not sure if...

I have recently noticed that Xilinx has changed the WebPACK download page: it now requires USER \ PWD login. I am not sure if you need to be a paying customer to get an account ? Just in case ! Once found, the files can be directly downloaded without logging in. Belo

hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform...

hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform Studio]. Since there are fixed possible sizes of BRAM which can be assigned,like for spartanIIe 2,4,8 KB First I tried executing with cache disabled-

I am trying to implement the baseband layer of Bluetooth on an FPGA, using Xilinx (project navigator) software. I have produced a...

I am trying to implement the baseband layer of Bluetooth on an FPGA, using Xilinx (project navigator) software. I have produced a simple maximal shift sequence and now want to Gaussian filter this. Has anybody used this software to complete this task before? If so could you

Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several...

Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several vendors like Xilinx(Picoblaze & Microblaze), @ltera(NIOS and NIOS-II) are making them. please do me a favor, I require some documents (articles

Just wondering if anyone has seen or tried one of the future electronics NIOS kits ...

Just wondering if anyone has seen or tried one of the future electronics NIOS kits http://www.futureelectronics.com/promos/ cyclone/ Any comments on these ? I've mostly only used xilinx so far.

Hi all, I am trying to interface a ps2 keyboard to the Xilinx Spartan2 FPGA I have. I have connected the keyboard to the Digilab...

Hi all, I am trying to interface a ps2 keyboard to the Xilinx Spartan2 FPGA I have. I have connected the keyboard to the Digilab DIO1 board and see no activity on the PS2D and PS2C pins when I use a logic analyser, and even when I pick inputs from the relevent FPGA pins and try

Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. ...

Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. I've been working on some open source tools to make FPGA work not totally unpleasant. fpgasm is to Verilog is what assembly language is to C++. With fewer than 10 reserved words, you can actually start hacking in minutes. Anyway, I hope you get a chanc...

Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600)...

Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600) with ethernet+flash+ram+CPLD. please visit my site at http://snaplogix.tripod.com for more informat