Forums Search for: Verilog
Execution unit in Verilog ?
Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have...
Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have (or know) a full design of RISC-style instructions execution unit in verilog. I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1
Re: VHDL and Verilog... the answer?
Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is...
Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is better: Verilog or VHDL?". But really I have not found a conclusive answer. why?, Each languages has advantages and disadvantages. However
Verilog code for an *bit Microprocessor
I am searching for verilog code for an 8-bit cpu. I'm trying to design my own 8 bit cpu with about 32-64 instructions based on...
I am searching for verilog code for an 8-bit cpu. I'm trying to design my own 8 bit cpu with about 32-64 instructions based on 8085 cpu. Urgent help is warrented. Thanks
fpgasm - a low-level design language for Xilinx FPGAs
Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. ...
Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. I've been working on some open source tools to make FPGA work not totally unpleasant. fpgasm is to Verilog is what assembly language is to C++. With fewer than 10 reserved words, you can actually start hacking in minutes. Anyway, I hope you get a chanc...
Implementation of LRU algo in verilog
Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is...
Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware. Thanks, Ruchi ------------------------------------ To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com ...
anyone has ps2 keyboard controller cores?
can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me...
can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me ? vhdl is better than in verilog thanks a lot
I want to buy FPGA and FPGA board
Hi, I am new to FPGA design. I am learning verilog and modelsim now. I want to implement my design for personal interest in...
Hi, I am new to FPGA design. I am learning verilog and modelsim now. I want to implement my design for personal interest in future. Any company of FPGA is OK for me. The most important is not expensive and easy to get the resource personally (eg. FPGA, download cable, programmer....
16 X 16 multiplier
Dear all, any one know how to design a 16X16 multiplier with one clock cycle? I know that some FPGA support embedded 16 X 16...
Dear all, any one know how to design a 16X16 multiplier with one clock cycle? I know that some FPGA support embedded 16 X 16 multiplier. However, is this operated in one clock cycle? Where can i get the layout/schematic/verilog design of this multiplier? Thanks
strange register behavior in Verilog blocks under Quartus II
Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get...
Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get an insight of FPGA and SoC design I downloaded the risc16f84 IP core from opencores.org and tried to get the small version of the PIC16F84 running on our an Altera FPGA board with a Flex 10K FPGA using th
LEON Verilog simulation
I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year ...
I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year project titled "Writing an instruction stream generator for a DUV". Currently, I am having problems finding a DUV. Could anyone tell me
SD card interface using FPGA
hai all , i am arun . i am working on interfacing SD card using FPGA. i am using SPI mode of communication to SD card . 1. i wrote the code in...
hai all , i am arun . i am working on interfacing SD card using FPGA. i am using SPI mode of communication to SD card . 1. i wrote the code in verilog for the identification mode , i generated clock frequency of 100 khz to SD clk then i kept the SD card clock cycle to run for 74 cycles with CS high 2. after lowered the CS to 0 and gave the command 0 i.e 40_00_00_00_00_95 (hex) to the...
Apple-I Software compatible system on Spartan3 starter kit
Hi, all. I build an Apple-I clone on the Spartran3 starter kit, and placed it on my web site. http://www.ip-arch.jp/indexe.html The all...
Hi, all. I build an Apple-I clone on the Spartran3 starter kit, and placed it on my web site. http://www.ip-arch.jp/indexe.html The all logics are written with SFL, but you can convert to verilog with my tool (sfl2vl) on the above site. The archive includes logic files under SFL folder Xilinx UCF and BMM and MEM files and BIT file under Xilinx folder and readme.txt (attached bel...
