Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios...

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios II system made by Altera. But i get the following error when I try to generate it. What error is this? On the other hand, what is the best way to save a stream of data into SDRAM? or would it be better if I made a soft memory for this purpose? Rega...

Has anyone ever tried to compile the LEON in Altera's Quartus II software? I'm having some trouble getting everything set up and...

Has anyone ever tried to compile the LEON in Altera's Quartus II software? I'm having some trouble getting everything set up and would appreciate any pointers.

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking...

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking for an educational board suitable for microprocessor designs and this seems to have the right peripherals.

** I am attempting to get information about the altera bitstream format ** I have already read ...

** I am attempting to get information about the altera bitstream format ** I have already read http://opencollector.org/news/Bitstream/ I wanted to make sure I wasn't missing something, is the information fo

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration...

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ARM processor (running uLinux), -- a 16M Synchronous DRAM (connected to FPGA and ARM) -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to...

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU...

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, it has the sliding register file windows technology. So I think it maybe support hardware multi-thread technology,but I can't find the relatial ma

What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor? ...

What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor?

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the...

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the clock cycles of a specific C program). Those who also do the similiar work of multi-cpu (XR-16) design: please give me your kind advice and share some useful ex

Hi Josh, I'd be interested to see your paper when you are finished. The Leon looks nice ... but I don't have a 800K gate...

Hi Josh, I'd be interested to see your paper when you are finished. The Leon looks nice ... but I don't have a 800K gate Virtex FPGA to play with. I'm using the BurchED FPGA board with the XC2S200. Are there any small 32 bit CPUs that will fit in a 200K gate FPGA ?

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get...

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get an insight of FPGA and SoC design I downloaded the risc16f84 IP core from opencores.org and tried to get the small version of the PIC16F84 running on our an Altera FPGA board with a Flex 10K FPGA using th

Hi, I'm trying to build some C code (separate .c files) and link the .o files together for Nios using the GNUPro tools that...

Hi, I'm trying to build some C code (separate .c files) and link the .o files together for Nios using the GNUPro tools that came with it. I keep getting errors that ld can't find crt0.o. So, I looked around the Nios documentation and couldn't find anything on c

Sir, I am doing a project on memory accelerator for ARM7TDMI. I have coded memory accelerator in VHDL. The memory used is a flash. I have LPC2129...

Sir, I am doing a project on memory accelerator for ARM7TDMI. I have coded memory accelerator in VHDL. The memory used is a flash. I have LPC2129 Arm processor with me. Does altera kit support for FPGA as well as ARM processor? or suggest any other option. kindly guide me. regards and thanx in advance sumana ------------------------------------ To post a message, send it to: f...@yahoogro...

If somebody needs a complete 6805 core, only send me an email; I'll be happy to share my design. It's a complete 6805 core (207...

If somebody needs a complete 6805 core, only send me an email; I'll be happy to share my design. It's a complete 6805 core (207 instructions, including MUL). Only 2 drawbacks: a) comments and an associated paper are written in Spanish. b) it's written using ALTERA AHDL, target

Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent...

Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent help is there any book, internet page, tutorial etc, which starts from scratch and goes up to design a simple cpu, including features such as, registers, in. sets, alu etc.... I am trying to prepare "Computer Architecture" class for computer e