Slew rate is the maximum rate of change of a signal with respect to time, typically expressed in volts per microsecond (V/µs) for analog signals or as a rise/fall time constraint for digital signals. It characterizes how quickly a circuit output or signal can transition between levels.
In practice
In op-amp circuits, slew rate is a key datasheet parameter. A classic LM741 is limited to roughly 0.5 V/µs, while a high-speed op-amp like the AD8397 can exceed 50 V/µs. If an input signal demands a faster transition than the op-amp can deliver, the output clips into a linear ramp rather than following the input, causing distortion. This matters when driving signals at higher frequencies or when amplifying fast transients in sensor or motor control applications.
On digital I/O, GPIO and bus driver slew rate is often configurable in the output driver hardware. On STM32 and many other Cortex-M MCUs, each GPIO pin commonly has a selectable speed or drive-strength setting (e.g., low, medium, high, very high speed), though the specific options and which pins support them vary by device and peripheral. Using the fastest setting on long PCB traces or cables increases radiated emissions and can cause ringing and crosstalk. Limiting GPIO slew rate is a common first step in meeting EMC requirements without adding external components.
In power electronics and motor control, slew rate directly affects switching losses versus EMI tradeoffs. A gate driver that switches a MOSFET or IGBT faster reduces switching losses but increases dV/dt and dI/dt, which stress gate insulation, generate conducted noise, and can trigger false turn-on in bridge topologies. Some gate driver ICs include adjustable slew rate control via an external resistor or integrated register, though many parts rely on fixed drive strength or more limited control schemes.
Slew rate limiting is also applied deliberately in software and control systems as a nonlinear filter to ramp a setpoint or command signal rather than stepping it instantaneously. This protects actuators from abrupt demand changes and reduces mechanical stress. The blog posts "Slew Rate Limiters: Nonlinear and Proud of It!" and "A Second Look at Slew Rate Limiters" cover this software-side application in detail, including the nuanced nonlinear behavior such limiters introduce into a control loop.
Discussed on EmbeddedRelated
Frequently asked
How do I calculate whether an op-amp's slew rate is fast enough for my application?
For a full-scale sinusoidal output, the minimum required slew rate is SR = 2 * pi * f * Vpeak, where f is the signal frequency and Vpeak is the peak output voltage. For example, a 10 V peak signal at 100 kHz requires at least 6.28 V/µs. Check your
op-amp datasheet and add margin, since the datasheet figure is typically measured under specific test conditions.
Why does my GPIO switching cause noise on nearby signals even though the logic levels are correct?
Fast
GPIO transitions create high dV/dt edges that couple capacitively into adjacent traces and radiate as
EMI. Reducing the GPIO slew rate setting in your
MCU's peripheral
registers (available on STM32, NXP Kinetis, and many other parts) slows the edge enough to reduce coupling and emissions, often without meaningfully affecting signal integrity for low-frequency logic.
What is the difference between slew rate and bandwidth?
Bandwidth is a small-signal, linear concept describing the frequency range over which gain stays within spec. Slew rate is a large-signal, nonlinear limit on how fast the output voltage can move, set by internal current limits charging compensation
capacitors. An
op-amp can have wide bandwidth but still slew-rate-limit on large, fast signals. Both constraints must be checked independently.
How does a software slew rate limiter work and when should I use one?
A software slew rate limiter clamps the per-update change of a setpoint or command to a maximum delta, effectively ramping the output instead of stepping it. It is useful for protecting motors, valves, and other actuators from abrupt demand changes, and for smoothing
DAC outputs. Because it introduces nonlinear behavior, it can complicate closed-loop stability analysis. The articles 'Slew Rate Limiters: Nonlinear and Proud of It!' and 'A Second Look at Slew Rate Limiters' on EmbeddedRelated cover the practical tradeoffs.
Does slew rate matter for I2C or SPI signals?
Yes, particularly for
I2C. The I2C specification limits rise and fall times, and because I2C uses
open-drain signaling with
pull-up resistors, the pull-up value is the primary tool for controlling edge rates. Some
MCU I2C peripherals also include slew rate control on their output drivers, but this is not universal. For
SPI, edge rate can matter even at lower clock speeds depending on trace length, impedance matching, and board noise environment; slew rate limiting on MOSI, MISO, and SCLK can prevent reflections and reduce radiated emissions when it is a concern.
Differentiators vs similar concepts
Slew rate is sometimes conflated with bandwidth or rise time. Rise time is a measured characteristic of a specific signal transition (the time to go from 10% to 90% of the final value), while slew rate is a rate-of-change limit expressed as V/µs. The two are related: a slew rate of SR V/µs on a signal swinging V volts implies a minimum rise time of roughly V/SR microseconds, but rise time can also be limited by RC parasitics or bandwidth, not only by slew rate. Bandwidth, in contrast, is a small-signal linear concept and does not capture the large-signal limiting behavior that slew rate describes.
