A pull-up resistor is a resistor connected between a signal line and a positive supply voltage (VCC or similar) that passively drives the line high when no active driver is asserting it low. It establishes a defined default logic state, preventing a floating input from reading unpredictably.
In practice
Pull-up resistors appear constantly in embedded designs: on open-drain buses like I2C (where both SDA and SCL require pull-ups to meet the open-drain signaling scheme), on active-low reset pins, on specific UART TX lines that idle high, and on GPIO inputs connected to buttons or switches that pull the line to ground when pressed. Without a pull-up (or pull-down) on a floating input pin, the pin can read random logic levels caused by capacitive coupling, nearby switching noise, or simply the indeterminate input impedance of the MCU buffer.
Resistor value selection involves a trade-off. A lower resistance (say 1k ohm) charges line capacitance faster and provides better noise immunity, but draws more static current when the line is pulled low by an open-drain driver. A higher resistance (say 100k ohm) minimizes current draw but slows edge rates and can cause signal integrity problems on fast or capacitively loaded lines. For I2C, the NXP I2C specification constrains pull-up values based on bus capacitance and speed: a 400 pF bus at 400 kHz typically calls for values in the 1k to 2k ohm range, while a lightly loaded 100 kHz bus commonly uses 4.7k or 10k ohm.
Many modern MCUs include configurable internal pull-up resistors on GPIO pins, eliminating the need for discrete parts in low-current, low-speed applications such as button inputs. Internal values typically range from around 20k to 100k ohm on many devices, though actual ranges vary by vendor, process, voltage, and configuration. They are generally too weak and too loosely specified for use on I2C buses or any line requiring controlled edge rates, so external resistors remain necessary in those cases. The blog post "Introduction to Microcontrollers - More On GPIO" covers the mechanics of enabling internal pull-ups on MCU pins.
On reset and configuration pins, a pull-up is often safety-critical: if the RESET or BOOT pin floats during power-up, the MCU may enter an unintended state. The blog post "How to Design Reliable Reset Circuits for Embedded Microcontrollers" discusses how pull-up values and layout interact with reset reliability. Even a seemingly simple pull-up to a reset pin deserves careful attention to supply ramp times and noise filtering.
Discussed on EmbeddedRelated
Frequently asked
What value pull-up resistor should I use for I2C?
It depends on bus speed and capacitance. The
I2C specification defines a maximum rise time that the pull-up RC must meet. For standard-mode (100 kHz) with low bus capacitance, 4.7k or 10k ohm is common. For fast-mode (400 kHz) or a board with multiple devices and longer traces, 1k to 2.2k ohm is more typical. Calculate the required value from the spec's rise-time limit and your estimated bus capacitance rather than picking a value by convention.
Can I use the MCU's internal pull-up instead of an external resistor?
For slow, non-critical signals like debounced button inputs, internal pull-ups (typically 20k to 100k ohm on most MCUs) are usually fine. For
I2C, open-drain level shifters, or any line where edge rate matters, internal pull-ups are generally too weak and too variable across temperature and process to be reliable. Use an external resistor in those cases.
Why is a floating input pin a problem, and does a pull-up actually fix it?
A CMOS input with nothing driving it sits in a high-impedance state, meaning small amounts of coupled noise or leakage current can swing the pin between logic levels. The resulting indeterminate state can cause spurious
interrupts, excessive current draw (because the input may sit near the switching threshold, causing unpredictable input buffer behavior), or undefined behavior. A pull-up (or
pull-down) provides a low-impedance DC path that holds the pin at a known logic level, fixing all of these problems as long as the resistor value is low enough relative to any leakage paths.
What is the difference between a pull-up and a bus-hold or keeper circuit?
A bus-hold (keeper) is an active circuit, typically a weak latch, that holds a line at whatever logic state it was last driven to. A pull-up always biases the line toward a specific fixed voltage regardless of the previous state. Pull-ups are predictable and passive; bus-holds are used in specific cases (like
FPGA I/O cells) to avoid floating states without always forcing a particular default level.
Does the pull-up resistor value affect power consumption?
Yes. When an open-drain or open-collector device pulls the line low, current flows continuously through the pull-up resistor from
VCC to ground. A 1k ohm pull-up on a 3.3 V line draws 3.3 mA when asserted low; a 100k ohm resistor draws only 33 uA. In battery-powered or low-power designs, using the highest resistance value that still meets signal integrity and timing requirements reduces quiescent current. Internal
MCU pull-ups (often 50k to 100k ohm) are generally favorable from a power standpoint for idle inputs.
Differentiators vs similar concepts
A
pull-down resistor serves the same purpose but connects the signal line to ground, establishing a default low state rather than a default high state. The choice between pull-up and pull-down depends on the logic convention of the signal: active-low signals (RESET, chip-select lines, open-drain buses) typically use pull-ups, while active-high signals that must default low use pull-downs. Pull-ups are more common in embedded work partly because open-drain topologies (
I2C, wired-AND logic, many reset circuits) inherently require them.
