embedded flash

On most general-purpose microcontrollers — STM32, nRF52, LPC, SAM, MSP430, PIC, AVR, and many others — the program itself executes directly from embedded flash (execute-in-place, XIP), though some devices boot from flash but run performance-critical code from RAM. The CPU fetches instructions over the internal bus at whatever width the flash interface supports, typically 32 or 64 bits, often with a prefetch buffer or instruction cache to mitigate the latency gap between flash and the CPU clock. On Cortex-M parts running above a device-dependent frequency threshold (commonly somewhere in the range of tens of MHz), wait states must be configured before increasing the clock, or the CPU will read unreliable or invalid data. This is a common early bringup mistake covered in startup code and discussed in resources like "Boot Sequence for an ARM based embedded system."

Embedded flash is organized into erasable sectors or pages, and the erase granularity varies widely across families. STM32F4 parts use large sectors (16 KB to 128 KB), making fine-grained in-application updates difficult without careful layout. STM32L0/L4 and nRF52 series use much smaller pages (2 KB or 4 KB), which is friendlier for storing configuration or performing over-the-air firmware updates. The "nRF5 to nRF Connect SDK migration via DFU over BLE" post illustrates how flash layout and erase constraints directly shape bootloader and DFU design.

Write and erase operations on embedded flash typically stall the bus, meaning the CPU cannot fetch instructions from flash while a write or erase is in progress — unless the MCU provides a second flash bank (dual-bank operation) or the code executing the write has been copied to RAM first. Failing to account for this can cause hard faults or lockups. Some devices, like the STM32G0/G4 and certain nRF53 parts, offer dual-bank configurations that can allow execution from one bank while the other is being erased or written, though seamless background operation depends on the specific part and configuration.

Endurance is finite: embedded flash is commonly rated for roughly 10,000 to 100,000 erase/write cycles per sector, though the actual rating varies by process node, temperature, voltage, and device family and may fall outside this range. Repeatedly writing to the same sector — for example, storing a frequently updated counter — will eventually wear it out. Wear-leveling schemes, whether implemented manually or via a library like NVS or LittleFS, spread writes across multiple sectors to extend flash lifetime.