DRAM (Dynamic Random-Access Memory) is a type of volatile semiconductor memory that stores each bit in a one-transistor, one-capacitor cell, requiring periodic refresh cycles to prevent data loss as the capacitor charge leaks away. It offers high density and relatively low cost per bit compared to SRAM, at the expense of more complex interfacing and access latency.
In practice
DRAM appears in embedded systems that need megabytes to gigabytes of working memory -- application processors running Linux, DSP pipelines, video frame buffers, and similar workloads. Microcontrollers aimed at simpler bare-metal tasks typically rely on on-chip SRAM instead, since the DRAM controller overhead and PCB routing complexity are impractical for small designs. DRAM becomes relevant once you move up to parts like the STM32MP1, i.MX RT series, Allwinner, or Rockchip SoCs, where an external DRAM chip is typically required for most variants.
The refresh requirement is the defining operational constraint. The memory controller must issue refresh commands at intervals specified by the DRAM datasheet (commonly every 64 ms for the full array, broken into per-row refreshes), regardless of whether the CPU is actively reading or writing. On systems with low-power modes, the designer must decide whether to put the DRAM into self-refresh (where the device handles its own refresh internally at reduced power) or to power it down entirely and accept that its contents will be lost.
Timing parameters dominate DRAM bring-up work. Values like CAS latency (CL), RAS-to-CAS delay (tRCD), row precharge time (tRP), and row active time (tRAS) must be programmed into the memory controller and matched to the specific chip in use. Errors in these parameters are a common source of subtle, intermittent data corruption -- a point directly relevant to the kinds of hardware bugs discussed in "The habitat of hardware bugs." Signal integrity, trace length matching, and termination also become significant at the speeds modern DRAM runs (DDR4 operates at typically 1600 to 3200 MT/s per pin on common parts, though speeds outside this range exist).
Modern DRAM commonly comes in several variants relevant to embedded work: LPDDR2/3/4/4X for mobile and embedded SoCs prioritizing power efficiency, DDR3/DDR4 for higher-performance application processor boards, and SDRAM or PSRAM for lower-complexity designs where a full DDR controller is not available. Some microcontrollers -- such as the STM32F4 and STM32H7 families -- include an FMC (Flexible Memory Controller) or FSMC peripheral capable of driving SDRAM directly, making modest DRAM expansion feasible without a dedicated external controller chip.
Frequently asked
Why does DRAM need refreshing but SRAM does not?
SRAM stores each bit in a cross-coupled latch (typically 6 transistors) that holds its state as long as power is applied. DRAM stores each bit as charge on a small
capacitor (1
transistor + 1 capacitor per cell), and that charge leaks away over time -- typically within milliseconds without intervention. The memory controller must periodically issue refresh commands to each row so that internal sense amplifiers restore the charge before it drops below the threshold needed to distinguish a logic 1 from a logic 0.
What is the difference between SDRAM, DDR SDRAM, and LPDDR?
SDRAM (Synchronous DRAM) transfers data on one edge of the clock, giving a transfer rate equal to the clock frequency.
DDR (Double Data Rate) SDRAM transfers on both edges, doubling bandwidth at the same clock. DDR generations (DDR3, DDR4, DDR5) increase clock speeds and reduce supply voltages incrementally. LPDDR is a low-power variant of DDR optimized for mobile and embedded SoCs, with features like per-bank refresh and deeper power-down states; LPDDR4X, for example, reduces I/O voltage to 0.6 V to cut dynamic power.
Can I use DRAM with a standard microcontroller, or do I need a dedicated memory controller?
You need a memory controller capable of handling the DRAM protocol -- issuing row activate, column read/write, precharge, and refresh commands at the correct timing. Some MCUs include this peripheral: the STM32F4 and STM32H7 families include an FMC that supports
SDRAM, and several i.MX RT parts include a SEMC for SDRAM or LPDDR. MCUs without such a peripheral cannot drive DRAM directly; PSRAM (pseudo-
SRAM) is sometimes used as an alternative because it hides the refresh behind an SRAM-compatible interface.
What happens to DRAM contents during low-power sleep modes?
If the memory controller stops issuing refreshes and the DRAM is not placed into self-refresh mode, the
capacitor charge leaks away and data is lost within milliseconds to tens of milliseconds, depending on temperature and the specific part. Most DRAM devices support a self-refresh command where internal circuitry handles refresh autonomously at reduced current (often a few hundred microamps for LPDDR parts). Systems that need to retain DRAM state across sleep must either keep the controller active and refreshing, or transition the DRAM to self-refresh before the SoC clock is gated down.
Why is DRAM timing so critical, and what goes wrong when it is misconfigured?
DRAM timing parameters define the minimum intervals required for internal operations -- charging sense amplifiers, settling bit lines, completing row activations. Violating them causes the cell to be read before it has driven the
data bus to a valid level, or a new row to be opened before the previous one is fully precharged. The result is intermittent bit errors that are data-pattern and temperature dependent, making them difficult to reproduce reliably. This class of subtle, hardware-rooted bug is discussed in 'The habitat of hardware bugs.' Always start from the timing values in the DRAM datasheet and verify with memory stress tests across operating temperature.
Differentiators vs similar concepts
DRAM is often contrasted with
SRAM and
Flash. SRAM uses a 6-
transistor latch per bit: no refresh needed, lower
latency, but much lower density and higher cost per bit -- it is the type used for on-chip
RAM in most microcontrollers. Flash is non-
volatile (retains data without power) but has limited write endurance and much slower random-write performance; it is used for code storage and data logging, not as working memory. PSRAM (pseudo-SRAM or cellular RAM) is a DRAM array with an integrated controller that presents an SRAM-compatible interface externally, hiding refresh from the host; it simplifies interfacing at the cost of occasional latency stalls when internal refresh occurs.
DDR SDRAM and LPDDR are specific DRAM sub-types optimized for bandwidth and power respectively, not distinct memory technologies.
