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Architecture Terms

Processor architectures, instruction sets, and core families (ARM Cortex-M, RISC-V, AVR, x86, MIPS).

23 terms in this category.

A B C D E F H L M N P R V
A
  • Atomic Operation An atomic operation is one that completes entirely or not at all, with no observable intermediate state visible to any other execution conte...
B
  • Big Endian Big-endian is a byte-ordering convention in which the most significant byte (MSB) of a multi-byte value is stored at the lowest memory addre...
  • Bitmask A bitmask is an integer value in which individual bits, or groups of bits, are used to select, set, clear, or test specific bits within anot...
C
  • CISC CISC (Complex Instruction Set Computer) is a processor architecture philosophy in which the CPU supports a large number of instructions, man...
  • CPLD A CPLD (Complex Programmable Logic Device) is a category of reconfigurable digital logic IC that uses an array of macrocells connected throu...
D
  • DSP A digital signal processor (DSP) is a processor architecture optimized for repetitive, numerically intensive operations on sampled data stre...
E
  • Endianness Endianness (also called byte order) describes the order in which the bytes of a multi-byte value are stored in memory or represented in a da...
F
  • Finite State Machine A finite state machine (FSM) is a computational model in which a system exists in exactly one of a finite number of defined states at any gi...
  • Fixed Point Fixed-point arithmetic is a method of representing fractional numbers using integers, where a scaling factor (the position of an implied bin...
  • Floating Point Floating-point is a numeric representation that encodes a value as a sign, a significand (mantissa), and an exponent, allowing the decimal p...
  • FPGA An FPGA (field-programmable gate array) is an integrated circuit containing a large array of configurable logic blocks, programmable interco...
  • FPU A floating-point unit (FPU) is a hardware block that executes IEEE 754 floating-point arithmetic operations -- addition, subtraction, multip...
H
  • Harvard Architecture Harvard architecture is a processor design in which instruction memory and data memory occupy separate address spaces and are accessed over ...
L
  • Little Endian Little-endian is a byte-ordering convention in which a multi-byte value is stored in memory with its least-significant byte (LSB) at the low...
M
  • MCU A microcontroller (MCU) is a single integrated circuit that combines a CPU core, on-chip flash or ROM for program storage, RAM, and a collec...
N
  • NVIC The Nested Vectored Interrupt Controller (NVIC) is a hardware interrupt controller integrated into ARM Cortex-M processors that manages exce...
P
  • PID Controller A PID controller is a closed-loop feedback algorithm that computes a corrective output by summing three terms: a proportional term (scaled d...
  • PLL A phase-locked loop (PLL) is a feedback control circuit that locks the phase and frequency of an output signal to a reference signal, typica...
R
  • Registers Registers are small, fixed-width storage locations built directly into a processor or peripheral, typically accessible in a single clock cyc...
  • RISC RISC (Reduced Instruction Set Computer) is a processor architecture philosophy that favors a small set of simple instructions, typically fix...
V
  • Vector Table A vector table is a region of memory containing a list of addresses (vectors) that the processor jumps to when handling exceptions or interr...
  • volatile (keyword) In C and C++, `volatile` is a type qualifier that tells the compiler a variable's value may change at any time outside the normal flow of th...
  • Von Neumann Architecture Von Neumann architecture is a computer design model in which program instructions and data share the same memory space and are accessed over...
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