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Discussion Groups | Rabbit-Semi | fun with UC/OS-II and system ISRs...
This is a group for folks designing and programming embedded systems using the Rabbit Semiconductor C-programmable microcontroller. Rabbit Semi is a spin-off from Z-World who makes a variety of embedded modules and tools. This group is not affiliated with either Rabbit or Z-World, but is a user forum for sharing ideas, asking questions, flaunting knowledge, and other typical user group stuff. The Rabbit is a powerful uC, supported by a full-featured C-compiler.
fun with UC/OS-II and system ISRs... - Julian Higginson - Jul 3 7:09:24 2008
Hello!
I'm currently investigating modifying a UC/OS-II based system, to add a new
task (a low level 1-wire comms handler on a normal I/O pin)
Anyway - this 1-wire handler will have wait states associated with different
operations, as you'd expect. And to implement these small wait states in
UC/OS-II, I'm going to have to do blocking waits at various points in my
task with OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). Now, looking at the
critical parts of 1-wire timing, I think that I can break these blocking
waits down so that the longest I'm locking anything else out is a shade over
70us.
>From what I understand of this UC/OS-II system, it basically switches
between tasks on system ticks, based on priority and if a task has requested
a wait or not. and it also has the system tick ISR off a timer that runs
every 15ms (in my system's case) which is heaps of time if I can guarantee I
only ever do a blocking wait right after an ISR tick (ie, straight after a
task wait?) and it has byte receive driven ISRs that go and grab a byte from
a serial port, and put them in a buffer that the SerXread() functions
access... and if this is the case, I think I'm safe to do a 70us blocking
wait without losing data, especially if I remove 115200 as a possible
baudrate (its never used, anyway). But the thing is, I don't know everything
about the low level interrupts and stuff happening in UC/OS-II - and weird
errors relating from something like this messing with other things I don't
know about could be pretty random, far between, and hard to fix. So I'm
hoping to be able to look at (or at least generate) an overview of all the
ISR functions my system uses, so I can work out how they all might react to
being held up a little bit.
Is there any documentation on low level ISR functions in dynamic C and
UC/OS-II?
I have the Dynamic C standard documentation, and the Dynamic C UC/OS-II
documentation, but haven't found anything about ISRs.
And I have the UC/OS-II "manual" but it's very generalized.
One thing that makes me hopeful is the code already uses OS_ENTER_CRITICAL()
and OS_ENTER_CRITICAL() in a few places anyway. without what looks like any
particular regard for the possibility of blocking anything.
Julian Higginson
Bruttour International P/L
http://www.bruttour.com.au
Ph: +612 9987 1581
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )
I'm currently investigating modifying a UC/OS-II based system, to add a new
task (a low level 1-wire comms handler on a normal I/O pin)
Anyway - this 1-wire handler will have wait states associated with different
operations, as you'd expect. And to implement these small wait states in
UC/OS-II, I'm going to have to do blocking waits at various points in my
task with OS_ENTER_CRITICAL() and OS_EXIT_CRITICAL(). Now, looking at the
critical parts of 1-wire timing, I think that I can break these blocking
waits down so that the longest I'm locking anything else out is a shade over
70us.
>From what I understand of this UC/OS-II system, it basically switches
between tasks on system ticks, based on priority and if a task has requested
a wait or not. and it also has the system tick ISR off a timer that runs
every 15ms (in my system's case) which is heaps of time if I can guarantee I
only ever do a blocking wait right after an ISR tick (ie, straight after a
task wait?) and it has byte receive driven ISRs that go and grab a byte from
a serial port, and put them in a buffer that the SerXread() functions
access... and if this is the case, I think I'm safe to do a 70us blocking
wait without losing data, especially if I remove 115200 as a possible
baudrate (its never used, anyway). But the thing is, I don't know everything
about the low level interrupts and stuff happening in UC/OS-II - and weird
errors relating from something like this messing with other things I don't
know about could be pretty random, far between, and hard to fix. So I'm
hoping to be able to look at (or at least generate) an overview of all the
ISR functions my system uses, so I can work out how they all might react to
being held up a little bit.
Is there any documentation on low level ISR functions in dynamic C and
UC/OS-II?
I have the Dynamic C standard documentation, and the Dynamic C UC/OS-II
documentation, but haven't found anything about ISRs.
And I have the UC/OS-II "manual" but it's very generalized.
One thing that makes me hopeful is the code already uses OS_ENTER_CRITICAL()
and OS_ENTER_CRITICAL() in a few places anyway. without what looks like any
particular regard for the possibility of blocking anything.
Julian Higginson
Bruttour International P/L
http://www.bruttour.com.au
Ph: +612 9987 1581
(You need to be a member of rabbit-semi -- send a blank email to rabbit-semi-subscribe@yahoogroups.com )