I'm trying to setup an SPI interface with the ADS1274.

I have the MSP in SPI Master mode.

The ADC is read only. So I'm triggering a dummy write on the DRDY pulse from the ADC.

The MSP then generate 8 SCLK pulses and fill the RX buffer. However the ADS1274 requires 1 andditional clock cycle before it clocks the data out.

So I'm always missong the MSB of the conversion.

To get round this I've bitbanged an addition SCLK cycle before the dummy transmit. But this is slow as I need to change the pin to a stadard output pin, apply a clock cyle then change the pin back to SCLK mode to allow the data read.

I'm running out of time to read all 24-bits of data before the next conversion. I'm actually getting every other conversion.

My thoughts were that it would be much easier if I could have SCLK running continuously but I dont know how to make that happen.

Any help would be appreciated.

Cheers

------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

Forgive me if this is too obvious but,,,

The fact that you didn't mention which mode you are using leads me to ask if you have you checked that you've matched SPI modes in teh two devices? I have seen this error when I've mixed SPI modes.

Regards,

Jim Dodd
Onset Computer Corporation

----- Original Message ----
> From: "f...@rocketmail.com"
> To: m...@yahoogroups.com
> Sent: Wed, November 4, 2009 5:19:07 AM
> Subject: [msp430] ADS1274 SPI interface - con
>
> I'm trying to setup an SPI interface with the ADS1274.
>
> I have the MSP in SPI Master mode.
>
> The ADC is read only. So I'm triggering a dummy write on the DRDY pulse from
> the ADC.
>
> The MSP then generate 8 SCLK pulses and fill the RX buffer. However the ADS1274
> requires 1 andditional clock cycle before it clocks the data out.
>
> So I'm always missong the MSB of the conversion.
>
> To get round this I've bitbanged an addition SCLK cycle before the dummy
> transmit. But this is slow as I need to change the pin to a stadard output pin,
> apply a clock cyle then change the pin back to SCLK mode to allow the data read.
> I'm running out of time to read all 24-bits of data before the next conversion.
> I'm actually getting every other conversion.
>
> My thoughts were that it would be much easier if I could have SCLK running
> continuously but I dont know how to make that happen.
>
> Any help would be appreciated.
>
> Cheers
>
>
>
> ------------------------------------

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

The ADS1274 is always in SPI slave, read only mode.

So currently I have the MSP set-up as master.

I have just tried another work around were I run the MSP in slave mode, generate the SCLK from the MSP SMCLK and loop it back into the MSP and the ADS.

Then I wait for the DRDY pulse from ADC to intitiate a read. This is also not working as the the time between the DRDY and the Read misses off a chunk of samples.

--- In m...@yahoogroups.com, Jim Dodd wrote:
>
> Forgive me if this is too obvious but,,,
>
> The fact that you didn't mention which mode you are using leads me to ask if you have you checked that you've matched SPI modes in teh two devices? I have seen this error when I've mixed SPI modes.
>
> Regards,
>
> Jim Dodd
> Onset Computer Corporation
>
> ----- Original Message ----
> > From: "francis.prime@..."
> > To: m...@yahoogroups.com
> > Sent: Wed, November 4, 2009 5:19:07 AM
> > Subject: [msp430] ADS1274 SPI interface - con
> >
> > I'm trying to setup an SPI interface with the ADS1274.
> >
> > I have the MSP in SPI Master mode.
> >
> > The ADC is read only. So I'm triggering a dummy write on the DRDY pulse from
> > the ADC.
> >
> > The MSP then generate 8 SCLK pulses and fill the RX buffer. However the ADS1274
> > requires 1 andditional clock cycle before it clocks the data out.
> >
> > So I'm always missong the MSB of the conversion.
> >
> > To get round this I've bitbanged an addition SCLK cycle before the dummy
> > transmit. But this is slow as I need to change the pin to a stadard output pin,
> > apply a clock cyle then change the pin back to SCLK mode to allow the data read.
> >
> >
> > I'm running out of time to read all 24-bits of data before the next conversion.
> > I'm actually getting every other conversion.
> >
> > My thoughts were that it would be much easier if I could have SCLK running
> > continuously but I dont know how to make that happen.
> >
> > Any help would be appreciated.
> >
> > Cheers
> >
> >
> >
> >
> >
> > ------------------------------------
> >
> >
> >
> >



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

You misunderstood the last question you were asked. He's not asking what read/write mode the chip is in. He's asking the clock/data mode. There are two settings for polarity and two for phase. You have to match the processor's mode to the chip's mode. If you don't match it, you will lose one end of the data byte. I just ran into this on a RTC.

You need to look closely at the processor's SPI operating info, and the chips, and really understand which of the 4 SPI clock/data modes you want to be in.

Lloyd

--- In m...@yahoogroups.com, "francis.prime@..." wrote:
>
> The ADS1274 is always in SPI slave, read only mode.
>
> So currently I have the MSP set-up as master.
>

------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

OK, well I believe I have the correct clock phase and polarity.

I have scoped the spi pins and applied a fullscale dc input into the ADC the output data is 24 bit in 2's complement mode. I know that the firt bit will be 0 (to indicate positive reading) then followed by all 1's. So I look at the clock and data output and I can see that the I am actually clocking two leading zeros and missing off the LSB. I can double check this by looking at the data recieved in the buffer by the debugger and it lines up. when I bit bang the first bit I do see the correct data in the buffer.

Your point maybe valid though I have got to what I think is the correct clock phase and polarity settings through luck/trial and error rather than judgement and I'll double check that.

--- In m...@yahoogroups.com, "lslonim2" wrote:
>
> You misunderstood the last question you were asked. He's not asking what read/write mode the chip is in. He's asking the clock/data mode. There are two settings for polarity and two for phase. You have to match the processor's mode to the chip's mode. If you don't match it, you will lose one end of the data byte. I just ran into this on a RTC.
>
> You need to look closely at the processor's SPI operating info, and the chips, and really understand which of the 4 SPI clock/data modes you want to be in.
>
> Lloyd
>
> --- In m...@yahoogroups.com, "francis.prime@" wrote:
> >
> > The ADS1274 is always in SPI slave, read only mode.
> >
> > So currently I have the MSP set-up as master.
>

------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

--- In m...@yahoogroups.com, "francis.prime@..." wrote:
>
> OK, well I believe I have the correct clock phase and polarity.
>

What have you set CKPH and CKPL to? Also, what is the delay from DRDY going low to the first transition on SCLK?

------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )

Make it easy for people to help you by posting the relevant code (and hardware configuration).

Michael K.

--- In m...@yahoogroups.com, "schultdw" wrote:
>
> --- In m...@yahoogroups.com, "francis.prime@" wrote:
> >
> > OK, well I believe I have the correct clock phase and polarity.
> > What have you set CKPH and CKPL to? Also, what is the delay from DRDY going low to the first transition on SCLK?
>

------------------------------------



(You need to be a member of msp430 -- send a blank email to msp430-subscribe@yahoogroups.com )