2106 | ADC | ARM7 | Atmel | Bootloader | CAN | CrossStudio | CrossWorks | DDS | ECos | Ethernet | ETM | FIFO | FLASH | FPGA | GCC | GDB | GNU | GNUARM | GPIO | I2C | IAP | IAR | JTAG | Kickstart | LCD | Linux | LPC | LPC-E2294 | LPC2000 | LPC2100 | LPC2104 | Lpc2106 | Lpc210x | LPC2114 | LPC2119 | LPC2124 | LPC2129 | Lpc2138 | LPC213x | LPC21xx | LPC2210 | LPC2212 | LPC2214 | LPC2292 | LPC2294 | LPC2xxx | LPC3128 | MCB2100 | Olimex | Philips | PWM | Rowley | RTC | RTOS | SPI | SSP | UART | UART0 | UART1 | ULINK | USB | Watchdog | Wiggler

I'm trying to setup an SSP port as SPI to interface with a 4M SPI Flash
memory chip, eg. M25P40. For a MEM write cycle, you must send 8 bit
opcode, 24 bit adr, and 8 bit data. For a MEM read cycle, you send 8
bit opcode, 24 bit adr, and then read 8 bit data.

How is this possible with the SSP/SPI setup of these LPC MCUs? They
only have 1 reg setting for "data size", 4-16 bits. But that does not
cover the requirement to send 32 bits to get 8 bits back of data. The
SSEL line must be held active during this entire time, and I don't see
how this is possible with the LPC SSP reg setup.

Unless I'm missing something, these LPC SSP/SPI modules just don't have
the flexibility to do this. Is there something I missed?

Chris.

------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

For a 24 bit addresses, usually you send 3 separate 8 bit partial
addresses, low, mid, and high. Then read status back.
--- In l...@yahoogroups.com, "sig5534" wrote:
>
> I'm trying to setup an SSP port as SPI to interface with a 4M SPI
Flash
> memory chip, eg. M25P40. For a MEM write cycle, you must send 8
bit
> opcode, 24 bit adr, and 8 bit data. For a MEM read cycle, you send
8
> bit opcode, 24 bit adr, and then read 8 bit data.
>
> How is this possible with the SSP/SPI setup of these LPC MCUs?
They
> only have 1 reg setting for "data size", 4-16 bits. But that does
not
> cover the requirement to send 32 bits to get 8 bits back of data.
The
> SSEL line must be held active during this entire time, and I don't
see
> how this is possible with the LPC SSP reg setup.
>
> Unless I'm missing something, these LPC SSP/SPI modules just don't
have
> the flexibility to do this. Is there something I missed?
>
> Chris.
>

------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

On Sat, 16 Aug 2008 13:24:00 -0000, you wrote:

>For a 24 bit addresses, usually you send 3 separate 8 bit partial
>addresses, low, mid, and high. Then read status back.
>--- In l...@yahoogroups.com, "sig5534" wrote:
>>
>> I'm trying to setup an SSP port as SPI to interface with a 4M SPI
>Flash
>> memory chip, eg. M25P40. For a MEM write cycle, you must send 8
>bit
>> opcode, 24 bit adr, and 8 bit data. For a MEM read cycle, you send
>8
>> bit opcode, 24 bit adr, and then read 8 bit data.
>>
>> How is this possible with the SSP/SPI setup of these LPC MCUs?
>They
>> only have 1 reg setting for "data size", 4-16 bits. But that does
>not
>> cover the requirement to send 32 bits to get 8 bits back of data.

You send two 16 bit words, and ignore the extra bits from the read.
>The
>> SSEL line must be held active during this entire time, and I don't
>see
>> how this is possible with the LPC SSP reg setup.

>From memory I think SSEL stays asserted if you send the data fast enough. The fifo means you can,
for example send two 16 bit words without waiting for the first to complete, and it gets sent as if
it was a 32 bit transfer.

However the easiest approach to SSEL may simply be to ignore the SSP module's SSEL functinality and
generate SSEL with an I/O pin ( which can of course be the same physical pin, just with a different
pin config register setting.

>> Unless I'm missing something, these LPC SSP/SPI modules just don't
>have
>> the flexibility to do this. Is there something I missed?
>>
>> Chris.
>>------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

>>You send two 16 bit words, and ignore the extra bits from the read.
>>From memory I think SSEL stays asserted if you send the data fast enough. The fifo means you can,
>>for example send two 16 bit words without waiting for the first to complete, and it gets sent as if
>>it was a 32 bit transfer.

>From what I read in the manual, the SSP works a little different than the SPI. The SPI only had SSEL as an input, so you had to manually drive it for Master mode. But in the SSP SSEL is I/O and it says it "activates the SSEL shortly before the data and deactivates after the data." The SSP has an 8 frame FIFO. So I think you are correct. I need to set the data size as 8 bits, than make 4 byte writes to it consecutively. 16b mode isn't the best when I have to deal with 24 bit sends.

Thanks.

Chris.
[Non-text portions of this message have been removed]
------------------------------------



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )