A word or two of thanks and some SPI info, (LPC2129) | LPC2000

..to those here who recently responded to my query about SPI/FIQ
interrupts with useful hints and even more useful examples.

Thanks to your help, I now have my SPI working OK, though it's a
little kludgy so far:

In the initialization, I 'manually' load up the RAM FIQ vector at
0x4000001C with a 'mov pc,r8' instruction word, then, in the
read/write/whatever functions, I switch to FIQ mode, load paramters
and set r8 to point at the required interrupt handler, then set off
the read/write by loading the SPI data register.

The interrupt handler runs with each interrupt, reading/writing bytes,
until a count has expired, at which time the handler disables the FIQ
by settting bit 10, (SPI), in the VICIntEnClear. The handler then
sets bit 1 in the VICSoftInt register and exits. This causes an IRQ
level 1 whose handler I have set up to signal a ctl semaphore. I
found out that this handler must explicitly clear the IRQ with a
'VICSoftIntClear=2;' to prevent the IRQ interrupt firing again
immediately the handler exits. The sending of the semaphore unit
enables my SPI handling thread to continue after the read/write call
is done.

Summary - my first experiment with ARM assembler actually works :)

I have a fully-functioning SPI interrupt driver. I have given some
detail above in case it might help others - you don't have to poll!

Thanks again, everyone who helped, (inc. Rowley/Crossworks).

Now I have to remove all the kludges and commented-out bad code

Next, I will try to load it into .fasttext section.

Rgds,
Martin

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Discussion Groups | LPC2000 | A word or two of thanks and some SPI info, (LPC2129)

A word or two of thanks and some SPI info, (LPC2129) - mjames_doveridge - Jul 4 12:23:52 2008