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Discussion Groups | LPC2000 | Problems with SSP
Discussion group dedicated to the Philips LPC2000 family of ARM MCUs
Problems with SSP - ajellisuk - Jun 3 7:28:32 2008
Hi
I'm trying to access an external flash memory chip (A25L16P) using
the SSP interface configured as an SPI interface. I have established
communications with the chip but the SSP interface is not receiving
the bytes in the correct order. I have observed the interface with a
logic analyser and the bytes are being sent from the FLASH ROM in the
correct order. I'm expexting to receive:
7Fh 37h 20h 25h
But I often see these bytes shifted round or with some bytes missing
eg:
37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
Does anyone know what could be going wrong?
Thanks in advance
Andrew Ellis
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
I'm trying to access an external flash memory chip (A25L16P) using
the SSP interface configured as an SPI interface. I have established
communications with the chip but the SSP interface is not receiving
the bytes in the correct order. I have observed the interface with a
logic analyser and the bytes are being sent from the FLASH ROM in the
correct order. I'm expexting to receive:
7Fh 37h 20h 25h
But I often see these bytes shifted round or with some bytes missing
eg:
37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
Does anyone know what could be going wrong?
Thanks in advance
Andrew Ellis
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: Problems with SSP - Chanchala Patil - Jun 3 9:15:20 2008
Are you erase your flash before write??
----- Original Message -----
From: ajellisuk
To: l...@yahoogroups.com
Sent: Tuesday, June 03, 2008 4:58 PM
Subject: [lpc2000] Problems with SSP
Hi
I'm trying to access an external flash memory chip (A25L16P) using
the SSP interface configured as an SPI interface. I have established
communications with the chip but the SSP interface is not receiving
the bytes in the correct order. I have observed the interface with a
logic analyser and the bytes are being sent from the FLASH ROM in the
correct order. I'm expexting to receive:
7Fh 37h 20h 25h
But I often see these bytes shifted round or with some bytes missing
eg:
37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
Does anyone know what could be going wrong?
Thanks in advance
Andrew Ellis
[Non-text portions of this message have been removed]
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
----- Original Message -----
From: ajellisuk
To: l...@yahoogroups.com
Sent: Tuesday, June 03, 2008 4:58 PM
Subject: [lpc2000] Problems with SSP
Hi
I'm trying to access an external flash memory chip (A25L16P) using
the SSP interface configured as an SPI interface. I have established
communications with the chip but the SSP interface is not receiving
the bytes in the correct order. I have observed the interface with a
logic analyser and the bytes are being sent from the FLASH ROM in the
correct order. I'm expexting to receive:
7Fh 37h 20h 25h
But I often see these bytes shifted round or with some bytes missing
eg:
37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
Does anyone know what could be going wrong?
Thanks in advance
Andrew Ellis
[Non-text portions of this message have been removed]
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: Problems with SSP - ajellisuk - Jun 3 9:34:46 2008
No, I'm not erasing the flash.
I'm sending the command to read the product id (9Fh). It appears that
there is some kind of framing error. On a logic analyser I can see
that the data is outputted from the FLASH ROM in the correct order,
it's when I read the SSPDR register in the LPC2148 that there is a
problem.
Is ther a way to ensure the SSPDR register is empty before I attempt
to read data from an external device?
Thanks
Andrew
--- In l...@yahoogroups.com, "Chanchala Patil" wrote:
>
> Are you erase your flash before write??
>
> ----- Original Message -----
> From: ajellisuk
> To: l...@yahoogroups.com
> Sent: Tuesday, June 03, 2008 4:58 PM
> Subject: [lpc2000] Problems with SSP
> Hi
>
> I'm trying to access an external flash memory chip (A25L16P)
using
> the SSP interface configured as an SPI interface. I have
established
> communications with the chip but the SSP interface is not
receiving
> the bytes in the correct order. I have observed the interface
with a
> logic analyser and the bytes are being sent from the FLASH ROM in
the
> correct order. I'm expexting to receive:
>
> 7Fh 37h 20h 25h
>
> But I often see these bytes shifted round or with some bytes
missing
> eg:
>
> 37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
>
> Does anyone know what could be going wrong?
>
> Thanks in advance
>
> Andrew Ellis
>
>
>
> [Non-text portions of this message have been removed]
>
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
I'm sending the command to read the product id (9Fh). It appears that
there is some kind of framing error. On a logic analyser I can see
that the data is outputted from the FLASH ROM in the correct order,
it's when I read the SSPDR register in the LPC2148 that there is a
problem.
Is ther a way to ensure the SSPDR register is empty before I attempt
to read data from an external device?
Thanks
Andrew
--- In l...@yahoogroups.com, "Chanchala Patil"
>
> Are you erase your flash before write??
>
> ----- Original Message -----
> From: ajellisuk
> To: l...@yahoogroups.com
> Sent: Tuesday, June 03, 2008 4:58 PM
> Subject: [lpc2000] Problems with SSP
> Hi
>
> I'm trying to access an external flash memory chip (A25L16P)
using
> the SSP interface configured as an SPI interface. I have
established
> communications with the chip but the SSP interface is not
receiving
> the bytes in the correct order. I have observed the interface
with a
> logic analyser and the bytes are being sent from the FLASH ROM in
the
> correct order. I'm expexting to receive:
>
> 7Fh 37h 20h 25h
>
> But I often see these bytes shifted round or with some bytes
missing
> eg:
>
> 37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
>
> Does anyone know what could be going wrong?
>
> Thanks in advance
>
> Andrew Ellis
>
>
>
> [Non-text portions of this message have been removed]
>
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: Re: Problems with SSP - Herbert Demmel - Jun 3 11:27:32 2008
Andrew,
this looks like being a typical timing problem. If you read (or
write) the SSPDR too late, you get a "shifted" value instead.
Lowering the clock speed of the SPI and/or reading writing the SPI
data register in time (possibly interrupt driven) should help.
I don't know which LPC you are using but not having a FIFO makes
things with SPI sometimes really difficult.
Herbert
At 13:34 03.06.2008 +0000, you wrote:
>No, I'm not erasing the flash.
>
>I'm sending the command to read the product id (9Fh). It appears that
>there is some kind of framing error. On a logic analyser I can see
>that the data is outputted from the FLASH ROM in the correct order,
>it's when I read the SSPDR register in the LPC2148 that there is a
>problem.
>
>Is ther a way to ensure the SSPDR register is empty before I attempt
>to read data from an external device?
>
>Thanks
>
>Andrew
>
>--- In l...@yahoogroups.com, "Chanchala Patil" wrote:
> >
> > Are you erase your flash before write??
> >
> > ----- Original Message -----
> > From: ajellisuk
> > To: l...@yahoogroups.com
> > Sent: Tuesday, June 03, 2008 4:58 PM
> > Subject: [lpc2000] Problems with SSP
> >
> >
> > Hi
> >
> > I'm trying to access an external flash memory chip (A25L16P)
>using
> > the SSP interface configured as an SPI interface. I have
>established
> > communications with the chip but the SSP interface is not
>receiving
> > the bytes in the correct order. I have observed the interface
>with a
> > logic analyser and the bytes are being sent from the FLASH ROM in
>the
> > correct order. I'm expexting to receive:
> >
> > 7Fh 37h 20h 25h
> >
> > But I often see these bytes shifted round or with some bytes
>missing
> > eg:
> >
> > 37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
> >
> > Does anyone know what could be going wrong?
> >
> > Thanks in advance
> >
> > Andrew Ellis
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
this looks like being a typical timing problem. If you read (or
write) the SSPDR too late, you get a "shifted" value instead.
Lowering the clock speed of the SPI and/or reading writing the SPI
data register in time (possibly interrupt driven) should help.
I don't know which LPC you are using but not having a FIFO makes
things with SPI sometimes really difficult.
Herbert
At 13:34 03.06.2008 +0000, you wrote:
>No, I'm not erasing the flash.
>
>I'm sending the command to read the product id (9Fh). It appears that
>there is some kind of framing error. On a logic analyser I can see
>that the data is outputted from the FLASH ROM in the correct order,
>it's when I read the SSPDR register in the LPC2148 that there is a
>problem.
>
>Is ther a way to ensure the SSPDR register is empty before I attempt
>to read data from an external device?
>
>Thanks
>
>Andrew
>
>--- In l...@yahoogroups.com, "Chanchala Patil"
> >
> > Are you erase your flash before write??
> >
> > ----- Original Message -----
> > From: ajellisuk
> > To: l...@yahoogroups.com
> > Sent: Tuesday, June 03, 2008 4:58 PM
> > Subject: [lpc2000] Problems with SSP
> >
> >
> > Hi
> >
> > I'm trying to access an external flash memory chip (A25L16P)
>using
> > the SSP interface configured as an SPI interface. I have
>established
> > communications with the chip but the SSP interface is not
>receiving
> > the bytes in the correct order. I have observed the interface
>with a
> > logic analyser and the bytes are being sent from the FLASH ROM in
>the
> > correct order. I'm expexting to receive:
> >
> > 7Fh 37h 20h 25h
> >
> > But I often see these bytes shifted round or with some bytes
>missing
> > eg:
> >
> > 37h 20h 25h 00h, or 00h 00h 7Fh 37h, or 00h 7Fh 37h 20h
> >
> > Does anyone know what could be going wrong?
> >
> > Thanks in advance
> >
> > Andrew Ellis
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: Re: Problems with SSP - Mukund Deshmukh - Jun 3 12:00:33 2008
> this looks like being a typical timing problem. If you read (or
> write) the SSPDR too late, you get a "shifted" value instead.
> Lowering the clock speed of the SPI and/or reading writing the SPI
> data register in time (possibly interrupt
With SSP/SPI it is always better to start with min speed, and once reliable
communication established, increase speed.
And yes putoff interrupt too, and wait for SPIF flag.
Hope this helps.
Warm Regards,
Mukund Deshmukh,
Beta Computronics Pvt Ltd.
10/1 IT Park, Parsodi,
Nagpur -440022 India.
Web site - http://betacomp.com
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
> write) the SSPDR too late, you get a "shifted" value instead.
> Lowering the clock speed of the SPI and/or reading writing the SPI
> data register in time (possibly interrupt
With SSP/SPI it is always better to start with min speed, and once reliable
communication established, increase speed.
And yes putoff interrupt too, and wait for SPIF flag.
Hope this helps.
Warm Regards,
Mukund Deshmukh,
Beta Computronics Pvt Ltd.
10/1 IT Park, Parsodi,
Nagpur -440022 India.
Web site - http://betacomp.com
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: Problems with SSP - "Thomas (Tom) M. Alldread" - Jun 4 12:41:18 2008
Greetings:
I think your problem is that the RX FIFO contains random data from
previous SSP transmit data. Every time clock pulses are sent the SSP
reads whatever data is on the MISO pin. I am using a different SPI slave
device than what you are using so your situation could be different. For
the device I am using I set up a simple loop that reads and discards
data from the SSDR until the FIFO is empty. I run this loop after
sending the read command but before sending the subsequent clock pulse
stream for extracting the data. This way the RX FIFO contains nothing
but data from the slave device.
I hope this helps.
--
Best Regards,
Tom Alldread
t...@telus.net
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
I think your problem is that the RX FIFO contains random data from
previous SSP transmit data. Every time clock pulses are sent the SSP
reads whatever data is on the MISO pin. I am using a different SPI slave
device than what you are using so your situation could be different. For
the device I am using I set up a simple loop that reads and discards
data from the SSDR until the FIFO is empty. I run this loop after
sending the read command but before sending the subsequent clock pulse
stream for extracting the data. This way the RX FIFO contains nothing
but data from the slave device.
I hope this helps.
--
Best Regards,
Tom Alldread
t...@telus.net
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Re: Problems with SSP - ksdoubleshooter - Jun 6 11:24:52 2008
After SSP initialization, flush the RX FIFO.
Jeff
--- In l...@yahoogroups.com, "Thomas (Tom) M. Alldread"
wrote:
>
> Greetings:
>
> I think your problem is that the RX FIFO contains random data
from
> previous SSP transmit data. Every time clock pulses are sent the
SSP
> reads whatever data is on the MISO pin. I am using a different SPI
slave
> device than what you are using so your situation could be
different. For
> the device I am using I set up a simple loop that reads and
discards
> data from the SSDR until the FIFO is empty. I run this loop after
> sending the read command but before sending the subsequent clock
pulse
> stream for extracting the data. This way the RX FIFO contains
nothing
> but data from the slave device.
>
> I hope this helps.
>
> --
> Best Regards,
> Tom Alldread
> tmall@...
>
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )
Jeff
--- In l...@yahoogroups.com, "Thomas (Tom) M. Alldread"
>
> Greetings:
>
> I think your problem is that the RX FIFO contains random data
from
> previous SSP transmit data. Every time clock pulses are sent the
SSP
> reads whatever data is on the MISO pin. I am using a different SPI
slave
> device than what you are using so your situation could be
different. For
> the device I am using I set up a simple loop that reads and
discards
> data from the SSDR until the FIFO is empty. I run this loop after
> sending the read command but before sending the subsequent clock
pulse
> stream for extracting the data. This way the RX FIFO contains
nothing
> but data from the slave device.
>
> I hope this helps.
>
> --
> Best Regards,
> Tom Alldread
> tmall@...
>
------------------------------------
(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )