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Hi, I need to fix the reset problem on some older
LPC2124, and need a very low freq crystal oscillator.

Did anybody try running the PLL with Crystal/Osc Fosc
around 3.68Mhz?? Is PLL stable at that range??

The datasheet and application note say PLL only
working in the 10-25MHz Fosc range.

(Note: I can get around with the 10Mhz-25Mhz fosc
requirement for ISP. Only checking if PLL is stable)

Regards



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

I have 5V part connected to LPC2148 GPIO. Unfortunately, the input of 5V
part has lower limit for VinH above 3,5V. Digital signals are generated
by LPC, the 5V part is input only (not bidirectional). I checked one
trick: I connected resistor between GPIO and 5V. Then I cleared IOPIN
bit and switched GPIO direction IODIR bit.

That's the logic:
To set 0V: GPIO = 0, IODIR = output
To set 5V: IODIR = input

So, the operating the GPIO at 5V is simply by writing IOPIN bit to 0 and
toggling it's IODIR bit.

Unfortunately, there's some stray capacitance at the input and I got
terrible rise times. I experimented around and got following results:

Rpullup = 10k; tr=2,3us
Rpullup = 1k; tr=250ns
Rpullup = 330ohm; tr=100ns

Here's my question: will GPIO survive and operate relible over long time
if I have 330 ohm pullup to 5V?

Marko



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Hi,

why don't you run a 24/7 test and see what happens?

It is real pitty that LPCs don't have Hi-Z IOs.

--- In l...@yahoogroups.com, Marko Pavlin wrote:
>
> Here's my question: will GPIO survive and operate relible over long
time
> if I have 330 ohm pullup to 5V?
>

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Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

Just one more thing. Did you use reply or post? All follow-ups are
going to be messed. Or is this some kind of yahoo feature?

BR,
Slawc
--- In l...@yahoogroups.com, Marko Pavlin wrote:
>
> I have 5V part connected to LPC2148 GPIO. Unfortunately, the input
of 5V
> part has lower limit for VinH above 3,5V. Digital signals are generated
> by LPC, the 5V part is input only (not bidirectional). I checked one
> trick: I connected resistor between GPIO and 5V. Then I cleared IOPIN
> bit and switched GPIO direction IODIR bit.
>
> That's the logic:
> To set 0V: GPIO = 0, IODIR = output
> To set 5V: IODIR = input
>
> So, the operating the GPIO at 5V is simply by writing IOPIN bit to 0
and
> toggling it's IODIR bit.
>
> Unfortunately, there's some stray capacitance at the input and I got
> terrible rise times. I experimented around and got following results:
>
> Rpullup = 10k; tr=2,3us
> Rpullup = 1k; tr=250ns
> Rpullup = 330ohm; tr=100ns
>
> Here's my question: will GPIO survive and operate relible over long
time
> if I have 330 ohm pullup to 5V?
>
> Marko
>



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

If you are in doubt you can use a transistor to drive the line to the
5V device so that 330 ohm on the collector are not an issue.
In this case you have the advantage of using the GPIO in the standard
fashion, with IOCLR and IOSET registers.
But if you have more than 2-3 lines connecting the LPC to 5V device
you should evaluate the use of an interface-logic, like the 74VHCT
family: they can be power supplied to 5V and have TTL compatible
inputs (input high level threshold of 2V).

Carlo

--- In l...@yahoogroups.com, Marko Pavlin wrote:
>
> I have 5V part connected to LPC2148 GPIO. Unfortunately, the input
of 5V
> part has lower limit for VinH above 3,5V. Digital signals are generated
> by LPC, the 5V part is input only (not bidirectional). I checked one
> trick: I connected resistor between GPIO and 5V. Then I cleared IOPIN
> bit and switched GPIO direction IODIR bit.
>
> That's the logic:
> To set 0V: GPIO = 0, IODIR = output
> To set 5V: IODIR = input
>
> So, the operating the GPIO at 5V is simply by writing IOPIN bit to 0
and
> toggling it's IODIR bit.
>
> Unfortunately, there's some stray capacitance at the input and I got
> terrible rise times. I experimented around and got following results:
>
> Rpullup = 10k; tr=2,3us
> Rpullup = 1k; tr=250ns
> Rpullup = 330ohm; tr=100ns
>
> Here's my question: will GPIO survive and operate relible over long
time
> if I have 330 ohm pullup to 5V?
>
> Marko
>

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


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--- In l...@yahoogroups.com, "unity0724" wrote:
>
> Hi, I need to fix the reset problem on some older
> LPC2124, and need a very low freq crystal oscillator.
>
> Did anybody try running the PLL with Crystal/Osc Fosc
> around 3.68Mhz?? Is PLL stable at that range??
>
> The datasheet and application note say PLL only
> working in the 10-25MHz Fosc range.
>
> (Note: I can get around with the 10Mhz-25Mhz fosc
> requirement for ISP. Only checking if PLL is stable)
>
> Regards

The PLL supports 1-50MHz. End user specifications has been limited
(to 10-25MHz) becuase the boot loader cannot cope with such a wide range.

Jaya



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--- In l...@yahoogroups.com, "jayasooriah"
wrote:
>
> --- In l...@yahoogroups.com, "unity0724" wrote:
> >
> > Hi, I need to fix the reset problem on some older
> > LPC2124, and need a very low freq crystal oscillator.
> >
> > Did anybody try running the PLL with Crystal/Osc Fosc
> > around 3.68Mhz?? Is PLL stable at that range??
> >
> > The datasheet and application note say PLL only
> > working in the 10-25MHz Fosc range.
> >
> > (Note: I can get around with the 10Mhz-25Mhz fosc
> > requirement for ISP. Only checking if PLL is stable)
> >
> > Regards
>
> The PLL supports 1-50MHz. End user specifications has been limited
> (to 10-25MHz) becuase the boot loader cannot cope with such a wide
> range.
>
> Jaya
>

Hello!
I'm only interested in:
- Getting that LPC2124 reset problem fixed! (or minimized)
- Checking if LPC2124 PLL is stable with 3.68MHz fosc

I Do NOT have any interest in the bootloader issue...
unless your bootloader is able to fix the LPC2124 reset
problem... :)

And, Sorry, where is that "The PLL supports 1-50MHz" from?
I cannot find it from user manual.
Could only find: "The PLL accepts an input clock frequency
in the range of 10 MHz to 25 MHz only" from user manual.

You happen to have another customer running the PLL below
10Mhz??

Regards



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

> That's the logic:
> To set 0V: GPIO = 0, IODIR = output
> To set 5V: IODIR = input

> Here's my question: will GPIO survive and operate relible over long
time
> if I have 330 ohm pullup to 5V?
>
> Marko
>

Hi Marko,

When the output is set to low, the input current (through gpio pin)
will be ~5V/330 Ohms = 15mA. Data sheet has +/-4mA, up to 40mA
for "short periods". I may work, but you will introduce other
problems that may not be obvious. For example, I would expect some
serious ground bounce without a very good pcb design. My short
answer would be no, not at 15mA .Find another solution. External
logic doesn't cost much and you know how it will behave.

Ian

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--- In l...@yahoogroups.com, "unity0724" wrote:

> Hello!
> I'm only interested in:
> - Getting that LPC2124 reset problem fixed! (or minimized)
> - Checking if LPC2124 PLL is stable with 3.68MHz fosc
>
> I Do NOT have any interest in the bootloader issue...
> unless your bootloader is able to fix the LPC2124 reset
> problem... :)
>
> And, Sorry, where is that "The PLL supports 1-50MHz" from?
> I cannot find it from user manual.
> Could only find: "The PLL accepts an input clock frequency
> in the range of 10 MHz to 25 MHz only" from user manual.
>
> You happen to have another customer running the PLL below
> 10Mhz??
>
> Regards

I don't know what your reset problem is. I was only responding to
your question alluded to by the title "PLL working with 3.68Mhz fosc".

I know that the PLL used in the LPC family is specified as 1-50 MHz.
Therefore it will work at 3.68 MHz. I have seen it in working outside
the 10-25 MHz range.

I am told that it was limited to 10-25 MHz in the user manual because
of boot loader support issues. I do not know what the issues are.

I can say however that I have not had any problems with my boot loader
with the full 1-50 MHz range.

Good luck.

Jaya

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "jayasooriah"
wrote:
>
> --- In l...@yahoogroups.com, "unity0724" wrote:
>
> > Hello!
> > I'm only interested in:
> > - Getting that LPC2124 reset problem fixed! (or minimized)
> > - Checking if LPC2124 PLL is stable with 3.68MHz fosc
> >
> > I Do NOT have any interest in the bootloader issue...
> > unless your bootloader is able to fix the LPC2124 reset
> > problem... :)
> >
> > And, Sorry, where is that "The PLL supports 1-50MHz" from?
> > I cannot find it from user manual.
> > Could only find: "The PLL accepts an input clock frequency
> > in the range of 10 MHz to 25 MHz only" from user manual.
> >
> > You happen to have another customer running the PLL below
> > 10Mhz??
> >
> > Regards
>
> I don't know what your reset problem is. I was only responding to
> your question alluded to by the title "PLL working with 3.68Mhz
fosc".
>
> I know that the PLL used in the LPC family is specified as 1-50
MHz.
> Therefore it will work at 3.68 MHz. I have seen it in working
outside
> the 10-25 MHz range.
>
> I am told that it was limited to 10-25 MHz in the user manual
because
> of boot loader support issues. I do not know what the issues are.
>
> I can say however that I have not had any problems with my boot
loader
> with the full 1-50 MHz range.
>
> Good luck.
>
> Jaya
>
Ooops,

I happen to know that the PLL is specified from 10-25 MHz input
only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
needed to make an external crystal run can support 1-50 MHz, not the
PLL.
We did test the PLL below 10 MHz and it locked reliably at least
down to 5 MHz. There were no thorough tests done below 5 MHz as this
is already way out of spec. What we could see, the jitter increased
a lot when using the PLL with 5 MHz input.
To get the reset problem fixed on the 2124, you actually need to
follow the instructions in the Errata Sheet, a double reset with the
given minimum time in between will fix it.

There is also a version LPC2124/00 which has the startup problem
fixed in hardware.

It is however correct that a lower external input frequency reduces
the likelyhood of the startup problem to occur.

nxp_apps



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---- Original Message ----
From: "nxp_apps"
To:
Sent: Thursday, October 19, 2006 5:04 PM
Subject: [lpc2000] Re: LPC2124's PLL working with 3.68Mhz fosc??

> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.

What is the story with these /00 chips (LPC2114,2119,2124,2129)? They are
only mentioned in the errata sheets, and it is hinted that they are not the
same as the "B" revision. Do they fix more bugs than "B", or even add
features like fast GPIO?

Karl Olsen



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

> What is the story with these /00 chips (LPC2114,2119,2124,2129)?
They are
> only mentioned in the errata sheets, and it is hinted that they are
not the
> same as the "B" revision. Do they fix more bugs than "B", or even
add
> features like fast GPIO?
>
> Karl Olsen
>
Karl,

the /00s have only one fix, that is the startup, nothing else fixed.
We are working on /01 versions that have all the fixes and will
include new features like the fast I/Os

Hope the /01s will be out in 1st quarter 07

nxp_apps

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

If you really have to live with only 1 resistor interface (rather than
some better sort of level translation), perhaps you could drive your IO
in a twho step process.
1/ Set Output to 1 (rise time to 3.5V is fast)
2/ Program IODIR to input (risetime 3.5v->5V resistor dependent)

Might get away with a larger resistor for the same overall Tr that way,
but it's pretty yuk.

________________________________

From: l...@yahoogroups.com [mailto:l...@yahoogroups.com]
On Behalf Of Marko Pavlin
Sent: Thursday, 19 October 2006 5:38 PM
To: l...@yahoogroups.com
Subject: [lpc2000] 5V GPIO output with single resistor

I have 5V part connected to LPC2148 GPIO. Unfortunately, the
input of 5V
part has lower limit for VinH above 3,5V. Digital signals are
generated
by LPC, the 5V part is input only (not bidirectional). I checked
one
trick: I connected resistor between GPIO and 5V. Then I cleared
IOPIN
bit and switched GPIO direction IODIR bit.

That's the logic:
To set 0V: GPIO = 0, IODIR = output
To set 5V: IODIR = input

So, the operating the GPIO at 5V is simply by writing IOPIN bit
to 0 and
toggling it's IODIR bit.

Unfortunately, there's some stray capacitance at the input and I
got
terrible rise times. I experimented around and got following
results:

Rpullup = 10k; tr=2,3us
Rpullup = 1k; tr=250ns
Rpullup = 330ohm; tr=100ns

Here's my question: will GPIO survive and operate relible over
long time
if I have 330 ohm pullup to 5V?

Marko

[Non-text portions of this message have been removed]

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "nxp_apps" wrote:

> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> needed to make an external crystal run can support 1-50 MHz, not the
> PLL.

You may be right that the 1-50 MHz was only for the crystal
oscillator. We ran devices at 1 MHz (for purposes I rather not
discuss) and while we were not looking specifically for PLL jitter,
the indications are that there were no problems with PLL capture or
sustained operation.

Jaya

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "jayasooriah" wrote:
>
> --- In l...@yahoogroups.com, "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>
Jaya,

that is an interesting data point. Would not have thought this works.
Thanks for this input.

Bob



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

Hi Jaya,

And if you were looking specifically for PLL jitter, where would you
look at?

When you say "sustained operation", do you mean over the entire
(specified) temp. range?
I am curious.

Best regards
Roger

--- In l...@yahoogroups.com, "jayasooriah" wrote:
>
> --- In l...@yahoogroups.com, "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "roger_lynx" wrote:
> And if you were looking specifically for PLL jitter, where would you
> look at?

Look at the eye pattern of any signal generated by MCU, for example
PWM. You need to ensure you are not synchronising exactly on PLL
divisor rate or it will appear jitter free. So if you are dividing by
16, sync on every 17th pulse and you get the full eye pattern in just
16 overlays.

> When you say "sustained operation", do you mean over the entire
> (specified) temp. range?

Not in this case. When DUT was subjected to arbitrary frequency and
duty ratios down to 1MHz, I do not rememner any of the observations
suggested that PLL capture failed. Thus I said it should work okay
with 3.68 MHz crystal.

I did not question the original information I got that said PLL range
is 1-50 MHz and that it is was specified to end user (in user manuals)
as 10-25 MHz.

Now that NXP_apps has clarified that 1-50 MHz applies to oscillator,
not PLL, anyone planning to run with less than 10 MHz crystal should
do burn in tests to be sure.

Jaya



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "jayasooriah"
wrote:
>
> --- In l...@yahoogroups.com, "roger_lynx" wrote:
> > And if you were looking specifically for PLL jitter, where would
you
> > look at?
>
> Look at the eye pattern of any signal generated by MCU, for example
> PWM. You need to ensure you are not synchronising exactly on PLL
> divisor rate or it will appear jitter free. So if you are
dividing by
> 16, sync on every 17th pulse and you get the full eye pattern in
just
> 16 overlays.
>
> > When you say "sustained operation", do you mean over the entire
> > (specified) temp. range?
>
> Not in this case. When DUT was subjected to arbitrary frequency
and
> duty ratios down to 1MHz, I do not rememner any of the observations
> suggested that PLL capture failed. Thus I said it should work okay
> with 3.68 MHz crystal.
>
> I did not question the original information I got that said PLL
range
> is 1-50 MHz and that it is was specified to end user (in user
manuals)
> as 10-25 MHz.
>
> Now that NXP_apps has clarified that 1-50 MHz applies to
oscillator,
> not PLL, anyone planning to run with less than 10 MHz crystal
should
> do burn in tests to be sure.
>
> Jaya
>

Regardless of how much testing you do, you clearly need to be aware
that following this recommendation is ignoring specific information
from NXP that problems have been seen with the PLL when the source
clock is outside the specified range of 10-25 Mhz.

Brendan.

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

--- In l...@yahoogroups.com, "Brendan Murphy"
> Regardless of how much testing you do, you clearly need to be aware
> that following this recommendation is ignoring specific information
> from NXP that problems have been seen with the PLL when the source
> clock is outside the specified range of 10-25 Mhz.

You clearly need to be aware that the objective specification and
recommended specifications to the end user can be very different.

Jaya



(You need to be a member of lpc2000 -- send a blank email to lpc2000-subscribe@yahoogroups.com )

>
> Ooops,
>
> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an
> inverter)
> needed to make an external crystal run can support 1-50 MHz, not
> the PLL.
> We did test the PLL below 10 MHz and it locked reliably at least
> down to 5 MHz. There were no thorough tests done below 5 MHz as
> this
> is already way out of spec. What we could see, the jitter
> increased
> a lot when using the PLL with 5 MHz input.
> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with
> the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.
>
> It is however correct that a lower external input frequency
> reduces
> the likelyhood of the startup problem to occur.
>
> nxp_apps
>

OK, Thanks,

These are some LPC2124 boards returned from customer... :(
I cannot change the circuit.
I will use 7.3Mhz fsoc, and wire a DIP8 WatchDog
Timer if I can find someway to "spider" it... :)

Regards

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


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