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LPC24xx ADC fifo   [3 Articles]

Hey ! First, i'd like to thank everyone for their help on my previous posts! your advices were crucial for me. Today, i'm working around adcs of lpc2478. I wonder if there ar...

UARTs and FIFO

Hello everybody. Has anybody used UARTS with FIFO enabled on LPC22xx? At first, I found this a big idea, but now that I'm trying to make it work it doesn't seem to be ...

high performance UART FIFO usage   [2 Articles]

I want to uart0 for tx long string with FIFO mode enable. what is the best performance wat to do that?I want the min time I must wait in this function. here is a simple function...

UART TX FIFO SIZE   [6 Articles]

Hi all members: I can get a Rx FIFO depth through FCR register,but how can I calculate the Tx FIFO size. According to the LPC2119 document,this CPU's UART is ...

SSP FIFO   [2 Articles]

...of course when I say that the manual doesn't mention the size of the SSP FIFo I'm obviously ignoring the very first page describing the SSP Features where it says there is...

USART0's FIFO empty question   [4 Articles]

I need to fill 16 byte each time i recieve INT.so i must sure the the FIFO is empty. For testing that the USART0's FIFO is fully empty is it enough to check the THRE or must...

TX FIFO   [17 Articles]

As soon as I write a single character to the THRE, Transmit holding register empty flag in U1LSR is cleared. Either the FIFO is not enabled or is set to '1', or thi...

REG: UART1 FIFO on LPC2104   [2 Articles]

Hi Friends, I am using lpc 2104. I am using IAR EMBEDDED WORKBENCH to develope program. I want to know about the Tx FIFO. I am writing values to UART1 TRANSMITTER HOL...

SSP on LPC2368

hello everyone now that I (hopefully) understand the SPI I need some help with the SSP interface in SPI mode. I have a LPC2368 which is connected to an audio-codec (TI's AI...

LPC2148, URAT and FIFO interrupts   [2 Articles]

Hi all, I'm playing with the uart fifo's on the LPC2148 and I have some problems getting the receiver buffer timeout interrupt to work. When I disable the fifo the interrupt...

UART1 and FIFO Reset (ISSUE)

Hello, After much fustration I appear to have solved most of my stability issues (although not all of them). I seem to have an undocumented issue with UART1 on the LP...

Disable RX on UARTS   [2 Articles]

Hello, I have an external circuit that echoes back the caracters that I am sending out of UARTs. Is there any way to disable RX while I'm transmitting (like Rx Enable ...

Software FLow Control With LPC UART   [12 Articles]

I am implementing software flow control and want to send an Xoff character.How can I Transmit a character without flushing the Transmit FIFO and without waiting for Transmit FIFO...

Re: LPCUSB Serial Flow Control

--- In l...@yahoogroups.com, "thirdshoedrops" wrote: > > For Bertrik or anybody else who's familiar with LPCUSB: is there flow > control built into USB and/or LPCUSB? > ...

How Erase LPC2129-UART RX FIFO   [2 Articles]

Hi The code written for rx data in LPC2129-uartO U0LCR = 0x83; U0DLL = 39; // baud rate = 9615 @ pclk = 6mhz U0FCR ...

SPI on LPC3180

Hi I was working on the LPC3180 and i am currently trying out the 2 SPI ports. getting one to receive and the other to transmit to each other. I understand that there is a FIF...

LPC2148 SSP FIFO manipulation

I am using the SSP on the LPC2148 as a buffered SPI interface to a custom CPLD design. I love the FIFO for transactions where I only need to write to the CPLD. But when I need...

SSP interrupts as SPIF behavior   [10 Articles]

Hello, I've some confusion as to how the interrupts on the SSP operate and don't seem to find any documentation regarding this. From the documentation I've found so far, th...

SSP LPC2148   [3 Articles]

Hello I have some questions concerning the SSP on the LPC2148. I need to speak with one ADC and one DAC. So therefore I need 2 slave select pins. But the LPC has only one. I know...

Re: Using SSP with 24bit transfers

At 05:24 PM 1/28/05 +0000, you wrote: >In looking at the SSP specification for the LPC2138, it can handle a >maximum frame size of 16 bits. Does anyone know of a wa...

UART Status Question   [2 Articles]

Hi, In reading the User Manual (for the LPC213x), I'm unclear on the meaning of the THRE bit in the LSR: Does this mean the entire Tx FIFO is empty? That is, I can write 16 ...

SSP: How to clear transmit FIFO   [9 Articles]

Hey, I want to clear the transmit-Fifo, to have a defined state. Knows anybody how to do do this? Regards Gerhard Unrecht [Non-text portions of this mes...

LPC213x UART1 RX/TX buffer   [2 Articles]

Anyone know if I turn off the FIFO (U1FCR bit 0 = 0) will I still get interrupts (if enabled) when a single character is received? Or does turning off the F...

LPC2138 TX FIFO full   [2 Articles]

If I enable the TX FIFO do I have to keep track of how many characters I've sent to THR so not to exceed 16? The transmit holding register empty bit only says it's not empty...

LPC214x: Can we really manage the SSP (SPI mode) in interrupt mode????   [3 Articles]

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that allows to trig an interrupt as so...

RE: SPI and SSP double buffered?

> On SPI, is the shift register different than the data register? In > other words, if I am a slave, can I put data in the SPI data register > any time even while a transition i...

LPC2129 A/D FIFO and accumulator   [2 Articles]

Hi Folks, Anyone know if there is a FIFO facility available for the A/D? Reference is made to it on p240 of the LPC2119/2129/2194/2292/2294 User Manual, bit 30...

Re: SSP/SPI on the LPC2478

Hi: The LPC2478 has a separate SPI module, that shares the same pins with the SSP0 module. The SSP module can work as a SPI, but it also has a FIFO for transmit and receive ...

Philips SPI1 confusion   [4 Articles]

Hello, I am working on some SPI routines on SSP port (lpc2148) and need some sanity check. Approach for sending data is quite standard and straightforward - - check if transmi...

Re: defecting to luminary?

Hi Ed > Have you measured/seen any limitations with the luminary ethernet, or is > this more of a thought experiment? While the 2kB FIFO seems a bit small > (and might p...

SPI, SSP Specification Differences

Greetings: I find the LPC2138 User Guide rather vague for the SPI, SSP peripherals. I wonder if there is additional support information for these peripherals that I d...

Re: Lost UART1 IRQ? (NOT COMPLETELY SOLVED)

--- In lpc2000@lpc2..., "vajper0" wrote: > Hi again! > > I just rewrote much of the UART code to slim it down and make it more > efficient. It was rather crap...

RE: Difference between SPI and SSP in LPC23xx   [3 Articles]

> -----Original Message----- > From: l...@yahoogroups.com > [mailto:l...@yahoogroups.com]On Behalf > Of varuzhandanielyan > Sent: Friday, May 25, 2007 12:34 AM > To...

Rx FIFO TRIGGER LEVEL(LPC2294)   [4 Articles]

I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive interrupt. For example if I set it for 4 bytes(bits 7:6=01 in the FIFO CONTROL REGISTER)and lets say tha...

Re: uart rx trigger level of receive 4 or 8 bytes in one interrupt.

> > My baud rate is 115200. You means that I had received those bytes, but in interrupt routine, I have no idea to deal with it. > > Could you mind send me your sample...

SSP issues with lpc24xx   [3 Articles]

Hi, when switching an lpc2000 design with a SPI slave to a lpc24xx I used the second set of MISO0 / MOSI0 / SSEL0 / SCK0 pins on P2[xx] expecting to be able to run my existi...

Detecting multiple key presses   [2 Articles]

Hi I have a project were I'm using an LPC2148, and a MAX7349 for the keypad interface. The MAX7349 has a FIFO register for storing key press events. I need to be able to ...

Re: i2s interrupt

It doesn't sound right. DMA is DMA, FIFO is FIFO. The interrupts for these two have no relationship. Have you checked the sample code bundle for I2S? It should have both DMA and...

Postpone interrupts on LPC21xx   [2 Articles]

Hi all, I have a software fifo that is being filled up by my main loop and then grabbed by an interrupts routine (TMR0). When entering the function that pushes a value onto ...