Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Sponsor
Ads
Discussion Groups
See Also
Discussion Groups | FPGA-CPU | Initial block ram contents
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Initial block ram contents - rtfinch35 - Dec 26 2:05:00 2001
|
How do I initialize the block ram contents without going through the PAR process every time ? Could someone please point me to more info. Thanks Rob http://www.birdcomputer.ca/ |
|
|
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Initial block ram contents - Christian Plessl - Jan 3 3:27:00 2002
|
> How do I initialize the block ram contents without going through the > PAR process every time ? Could someone please point me to more info. What kind of devices your are using? If you are using Xilinx Virtex you might use the Xilinx JBits Java class library for modifying bitstreams. You can get the tool for free from Xilinx. Using Jbits you can change the initial value of your BlockRAMS without any PAR. Regards, Christian |
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )