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Discussion Groups | FPGA-CPU | Cypress Samples First 2.5Gbit/sec Programmable PHY
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Cypress Samples First 2.5Gbit/sec Programmable PHY - Sean Jensen_Grey - Apr 3 20:16:00 2001
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Cypress Semiconductor Corp. today made available samples of the first chip from its family of programmable serial interface (PSI) backplane chips, claiming it is the first 2.5Gbit/sec programmable PHY. Cypress' PSI2G100 combines a 2.5 Gbit/sec serial link, 100k gates of programmable logic, and 0.5Mbit of communications memory, targeting system backplanes across a broad range of market segments, including InfiniBand. For more... http://article.ElectronicNews.com/UM/T.ASP?A5.11.225.9.40834604 So now Cypress, Altera and Xilinx do or will have > 1 Gbps links built into their chips. Nice. http://www.cypress.com/press/releases/210403.html http://www.altera.com/corporate/press_box/releases/pr-mercury_ship.html And the upcoming Xilinx Virtex II Pro |
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