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I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core.

So I started over at OpenCores and downloaded a DDR core but I haven't even begun to study it. Instead I went to the datasheet...

I notice that it takes 2 clocks to get the first word from memory. Then I can get a word every 1/2 clock. It's that initial 2 clocks that is bothering me. If I read randomly, I can count on at least 2 clocks of latency.

Is the idea to implement some kind of cache such that I read a burst into a page cache? Then, I suppose I need to have some kind of map to keep track of pages in cache, etc. I'm thinking that writes might not be cached (write through). Or maybe they are delayed until a page is swapped out (it's dirty).

My question is kind of general. Is this what everybody is doing with DDR RAM? Or are they just running such a fast RAM clock that, from the point of view of the CPU core, RAM is still pretty fast?

Any reference documents (other than the datasheet) that might get me started?

Richard

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On Fri, 2 Oct 2009, rtstofer wrote:

> Date: Fri, 02 Oct 2009 18:57:02 -0000
> From: rtstofer
> Reply-To: f...@yahoogroups.com
> To: f...@yahoogroups.com
> Subject: [fpga-cpu] Using DDR RAM
>
> I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of
> DDR RAM. They don't provide a controller core.
>
> So I started over at OpenCores and downloaded a DDR core but I haven't even
> begun to study it. Instead I went to the datasheet...
>
> I notice that it takes 2 clocks to get the first word from memory. Then I
> can get a word every 1/2 clock. It's that initial 2 clocks that is
> bothering me. If I read randomly, I can count on at least 2 clocks of
> latency.
>
> Is the idea to implement some kind of cache such that I read a burst into a
> page cache? Then, I suppose I need to have some kind of map to keep track
> of pages in cache, etc. I'm thinking that writes might not be cached (write
> through). Or maybe they are delayed until a page is swapped out (it's
> dirty).
>
> My question is kind of general. Is this what everybody is doing with DDR
> RAM? Or are they just running such a fast RAM clock that, from the point of
> view of the CPU core, RAM is still pretty fast?

Someone said "All programming is an exersize in caching" This also goes for
computer development.

DRAM access especially when page boundaries are crossed is still really slow.
modern CPUs may spin for 100s of clocks waiting for a new line of cache data
from the DRAM in this case. In fact DRAM transfer rates have gone up by a
factor of around 1000 since the first DRAMS but the random access time has
only been sped up by a factor of 10 or so. Even with a FPGA CPU, SDRAM is just
a cache filler...

>
> Any reference documents (other than the datasheet) that might get me
> started?
>
> Richard

Peter Wallace
Mesa Electronics

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If I remember correctly, I saw some benchmark from way back when, with best
processors at the time being P4-2.2GHz, P3-1.4GHz and
AMD-something-in-between, 1.6GHz or so, I think it was SpecInt 2000 with vpr
for the test. P3 had regular SDRAM, AMD had DDR SDRAM and P4 was one of
those unfortunate ones to have RLDRAM or something like that. P3 was the
fastest, AMD was next and P4 finished last despite of having the highest raw
clock frequency. P3 had least amount of RAM, so RAM size was not an issue,
just the RAM architecture. Even P3 at 1.26GHz was faster than P4 or AMD.

-----Original Message-----
From: f...@yahoogroups.com [mailto:f...@yahoogroups.com]On Behalf
Of Peter C. Wallace
Sent: Friday, October 02, 2009 2:33 PM
To: f...@yahoogroups.com
Subject: Re: [fpga-cpu] Using DDR RAM
On Fri, 2 Oct 2009, rtstofer wrote:

> Date: Fri, 02 Oct 2009 18:57:02 -0000
> From: rtstofer
> Reply-To: f...@yahoogroups.com
> To: f...@yahoogroups.com
> Subject: [fpga-cpu] Using DDR RAM
>
> I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16
of
> DDR RAM. They don't provide a controller core.
>
> So I started over at OpenCores and downloaded a DDR core but I haven't
even
> begun to study it. Instead I went to the datasheet...
>
> I notice that it takes 2 clocks to get the first word from memory. Then
I
> can get a word every 1/2 clock. It's that initial 2 clocks that is
> bothering me. If I read randomly, I can count on at least 2 clocks of
> latency.
>
> Is the idea to implement some kind of cache such that I read a burst
into a
> page cache? Then, I suppose I need to have some kind of map to keep
track
> of pages in cache, etc. I'm thinking that writes might not be cached
(write
> through). Or maybe they are delayed until a page is swapped out (it's
> dirty).
>
> My question is kind of general. Is this what everybody is doing with DDR
> RAM? Or are they just running such a fast RAM clock that, from the point
of
> view of the CPU core, RAM is still pretty fast?

Someone said "All programming is an exersize in caching" This also goes
for
computer development.

DRAM access especially when page boundaries are crossed is still really
slow.
modern CPUs may spin for 100s of clocks waiting for a new line of cache
data
from the DRAM in this case. In fact DRAM transfer rates have gone up by a
factor of around 1000 since the first DRAMS but the random access time has
only been sped up by a factor of 10 or so. Even with a FPGA CPU, SDRAM is
just
a cache filler...

>
> Any reference documents (other than the datasheet) that might get me
> started?
>
> Richard
>
>
>
>

Peter Wallace
Mesa Electronics

(\__/)
(='.'=) This is Bunny. Copy and paste bunny into your
(")_(") signature to help him gain world domination.

[Non-text portions of this message have been removed]

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--- In f...@yahoogroups.com, "rtstofer" wrote:

> I notice that it takes 2 clocks to get the first word from memory. Then I can get a word every 1/2 clock. It's that initial 2 clocks that is bothering me. If I read randomly, I can count on at least 2 clocks of latency.

This 2 clocks is only, if you are on the right page already, right ?

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Hi Richard,

rtstofer wrote:
> I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core.
>
> So I started over at OpenCores and downloaded a DDR core but I haven't even begun to study it. Instead I went to the datasheet...
>
> I notice that it takes 2 clocks to get the first word from memory. Then I can get a word every 1/2 clock. It's that initial 2 clocks that is bothering me. If I read randomly, I can count on at least 2 clocks of latency.
>
> Is the idea to implement some kind of cache such that I read a burst into a page cache? Then, I suppose I need to have some kind of map to keep track of pages in cache, etc. I'm thinking that writes might not be cached (write through). Or maybe they are delayed until a page is swapped out (it's dirty).
>
> My question is kind of general. Is this what everybody is doing with DDR RAM? Or are they just running such a fast RAM clock that, from the point of view of the CPU core, RAM is still pretty fast?
>
> Any reference documents (other than the datasheet) that might get me started?
>
> Richard
>
The DDR controller on open cores is very basic, but if you follow the
link to the company who is offering the commercial version, you will
find a detailed description of how the commercial controller core works.
The 2 clock delay is dependent on the configuration of the DDR. You can
clock the DDR faster if you use a 2.5 clock delay. I was study the
Micron data sheet fairly closely a month or two ago, but I have
forgotten the details.

First off you have to initialize the SDRAM with a configuration start up
procedure. I think the idea then is to do a row address strobe first,
which is called an Activate cycle, then a clock or two later you can do
a burst read or write cycle within a column. The data is actually
delayed a few clock cycles from the read and write request. If you want
to do a write after a read, you have to terminate the read cycle, (with
a precharge ?) then initiate a new write cycle.

The DDR is pipelined, so you can actually overlay some of the precharge
and activate cycles I think. To overcome having to terminate and
reinitiate a memory access, the chips usually have 4 banks that you can
access. I think the idea is that you can interleave bank accesses, so
for instance, you can be reading from one bank and writing to another
(others might care to correct me on that if I'm wrong). There are also
issues with auto refresh, which you might have to terminate the read or
write access cycle to perform.

I came up against that barrier with my 6809 design on the XESS board.
Although the SDRAM clocks at 100MHz, it takes 6 to 8 cycles for each
random access, so yes, you really need to use cache to get any speed out
of it. That is where dual ported block RAM comes to the rescue. If you
asked me about it a few months ago, I might have been able to give you a
more coherent answer.

Check out the data sheet for the chip. There are a number of different
ways you can use the SDRAMs to optimize them for the CPU design you are
using.

John.

--
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http://members.optusnet.com.au/jekent

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--- In f...@yahoogroups.com, John Kent wrote:

> I came up against that barrier with my 6809 design on the XESS board.
> Although the SDRAM clocks at 100MHz, it takes 6 to 8 cycles for each
> random access, so yes, you really need to use cache to get any speed out
> of it. That is where dual ported block RAM comes to the rescue. If you
> asked me about it a few months ago, I might have been able to give you a
> more coherent answer.
>
> Check out the data sheet for the chip. There are a number of different
> ways you can use the SDRAMs to optimize them for the CPU design you are
> using.
>
> John.
>

Hi John,

I have been thinking about the instruction cache and perhaps doing something like fetching 16 words per access. Basically, I would just mask off the lower 4 bits of the address and start a fetch into BlockRAM. As soon as I have the word the CPU wants, I can let it proceed while I grab the remainder of the block.

Nothing very sophisticated. The idea of wide fetches has been around for a very long time.

Interleaving is another very old idea. I haven't read enough of the datasheet to see if that is helpful.

I think for my simple projects, DDR is going to be the long way around. I'm looking at the Spartan 3E (500k) device because it comes in a PQ208 package that I might actually be able to mount. I can add a simple SRAM and I'm in business. Or maybe the Spartan 3 (400k) in the TQ144 package.

Richard

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This bounced

John Kent wrote:
>
> rtstofer wrote:
>> Hi John,
>>
>> I have been thinking about the instruction cache and perhaps doing
>> something like fetching 16 words per access. Basically, I would just
>> mask off the lower 4 bits of the address and start a fetch into
>> BlockRAM. As soon as I have the word the CPU wants, I can let it
>> proceed while I grab the remainder of the block.
>>
>> Nothing very sophisticated. The idea of wide fetches has been around
>> for a very long time.
>>
>> Interleaving is another very old idea. I haven't read enough of the
>> datasheet to see if that is helpful.
>>
>> I think for my simple projects, DDR is going to be the long way
>> around. I'm looking at the Spartan 3E (500k) device because it comes
>> in a PQ208 package that I might actually be able to mount. I can add
>> a simple SRAM and I'm in business. Or maybe the Spartan 3 (400k) in
>> the TQ144 package.
>>
>> Richard
>>
> Hi Richard,
>
> There is the Xilinx Memory Interface Generator (MIG 2.1). I notice
> Xilinx are running a Webinar on the memory interface in the Virtex 6
> and Spartan 6 on Tuesday. It would be interest to see, but it's at
> 11am US EDT or 2am in the morning Australian EDST time.
>
> I don't think you said what CPU you were using the memory for. What
> size address bus are you using ? With the block RAM, I assume its a
> matter of storing and comparing the high order address in the cache as
> well as the data, to determine if the cache entry is valid. You could
> buffer 16 words, but if you are using a burst access you are limited
> to 2, 4 or 8 words. Given that the block RAM is going to be larger
> than 16 words, you may as well use it as a full blown cache. I was
> looking at designing a 4 way (set ?) associative cache that worked
> with the (tag ?) cache and allowed you to cache memory in 4 different
> address ranges.
>
> I was having a discussion with Tommy Thorn on this list back in April
> this year about his MIPS compatible YARI CPU that used 4-way
> associative instruction and data cache. That might give you some
> design clues.
>
> http://yari.thorn.ws/YARI/Introduction.html
>
> I've seen very little activity on this list since then. I hope my
> email address has been working.
>
> John.
>

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--- In f...@yahoogroups.com, John Kent wrote:
>
> This bounced
>
> John Kent wrote:
> > Hi Richard,
> >

> > I don't think you said what CPU you were using the memory for. What
> > size address bus are you using ? With the block RAM, I assume its a
> > matter of storing and comparing the high order address in the cache as
> > well as the data, to determine if the cache entry is valid. You could
> > buffer 16 words, but if you are using a burst access you are limited
> > to 2, 4 or 8 words. Given that the block RAM is going to be larger
> > than 16 words, you may as well use it as a full blown cache. I was
> > looking at designing a 4 way (set ?) associative cache that worked
> > with the (tag ?) cache and allowed you to cache memory in 4 different
> > address ranges.
> >
> > John.

I bought the Spartan 3E Starter Board from Digilent because it is the basis of the latest Pacman arcade design. This is the very same project I didn't finish years ago when I bought the BurchEd board. I got as far as getting the T80 core to run, added a couple of Compact Flash devices and brought up CP/M. Great fun!

For the last 3 or 4 years I have been using the Spartan 3 Starter Board because, among other things, it has SRAM. It is also available with 1000k gates which is useful since my VHDL looks like it was written by a kindergartener with crayons.

As you may recall, I got the IBM 1130 emulation to run on that board and since then I have also gotten a PDP11-xx to run. The xx would be -40 if I had the MMU working. As it is, it runs RTL fairly well. I want the -40 version so I can run Unix V6.

The only reason I brought up the DDR question is that the 3E board has DDR but no SRAM. I was wondering if I could actually use the board for something other than an arcade machine. I was going to build a one-off PCB for the machine and I would have the 3E board for something else. But, given the lack of SRAM, maybe it is better to just bury the board inside the cabinet and go back to what I know; the Spartan 3 board. SRAM is good!

I have no idea where I am going with all this but I had thought to port both of my projects. I think I'll abandon that idea. I just keep bumping into things and sometimes my projects work out.

Richard

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rtstofer wrote:
> I bought the Spartan 3E Starter Board from Digilent because it is the basis of the latest Pacman arcade design. This is the very same project I didn't finish years ago when I bought the BurchEd board. I got as far as getting the T80 core to run, added a couple of Compact Flash devices and brought up CP/M. Great fun!
>
> For the last 3 or 4 years I have been using the Spartan 3 Starter Board because, among other things, it has SRAM. It is also available with 1000k gates which is useful since my VHDL looks like it was written by a kindergartener with crayons.
>
> As you may recall, I got the IBM 1130 emulation to run on that board and since then I have also gotten a PDP11-xx to run. The xx would be -40 if I had the MMU working. As it is, it runs RTL fairly well. I want the -40 version so I can run Unix V6.
>
> The only reason I brought up the DDR question is that the 3E board has DDR but no SRAM. I was wondering if I could actually use the board for something other than an arcade machine. I was going to build a one-off PCB for the machine and I would have the 3E board for something else. But, given the lack of SRAM, maybe it is better to just bury the board inside the cabinet and go back to what I know; the Spartan 3 board. SRAM is good!
>
> I have no idea where I am going with all this but I had thought to port both of my projects. I think I'll abandon that idea. I just keep bumping into things and sometimes my projects work out.
>
> Richard
>
Hi Richard,

Yes, I remember you sending me the code for the Z80 CP/M system on the
B5-X300 board. The boot up system was quite easy. OK on using the 1000K
gate Spartan 3 starter board. An internet friend used the System09 CPU
core to build a FPGA CoCo3 using that board. he wrote most of it in
verilog.

A friend from the Flex users group sent me this:

http://alexfreed.com/FPGApple/CB/System09.html

Carte Blanche is an FPGA-based card for the Apple II that has just become available

http://www.applelogic.org/CarteBlanche.html

The system09 for the Spartan 3E500 board just uses Block RAM. There is
enough RAM for monitor ROM, VDU and 32KBytes of user RAM, although I
need another 8KBytes of RAM to run the Flex Operating System.

Ok on the PDP-11 design. Sounds pretty good. An acquaintance from the
list sent me his PDP-8 design which I was playing with a few years ago
on the B5-X300 board. I think I have told you about that some time ago.
There were a few friends who were looking at interfacing the FPGA PDP-8
to some original DEC interface boards. I have lost touch with them, so
I'm not sure what they are up to now.

I have two 3S500E boards and I bought a VDEC-1 video digitizer board to
do some image processing on one of them. I would have liked to couple
two of the boards together to do stereo vision, but there are not enough
spare pins to pipe the video stream between the two boards. I came up
against the same problem as you with the lack of DDR controller although
I have not tried using the MIG2.1.

Stereopsis can be performed in a raster scan fashion, which is fairly
efficient for DDR as you can buffer a complete scan line in one column
access, but if you want to perform non raster accesses, as might be the
case for say warping using back projection, the bandwidth of SDRAM
becomes a problem, and you have to work out efficient caching strategies
to overcome the bottle neck.

I'm still using ISE and EDK 7.1 and 8.1. I can't really afford to be
upgrading EDK each time Xilinx make a new release. I did download
webpack ISE 11 the other day but I have not installed it yet. I am told
they have removed support for the Spartan 2 so I'll need to maintain the
old versions if I want to still work on the BurchED boards. The low cost
boards from most of the vendors still seem to be using the Spartan 3. I
haven't seen much around for the more recent Spartan FPGAs, but then I
have not really been looking.

Anyway, I better get on with my work.
Talk soon.

John.

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Hi Richard,

> As you may recall, I got the IBM 1130 emulation to run on that board
> and since then I have also gotten a PDP11-xx to run. The xx would be
> -40 if I had the MMU working. As it is, it runs RTL fairly well. I
> want the -40 version so I can run Unix V6.

very nice! If I remember correctly, the MMU of the -40 isn't
that complicated, so that the effort of implementing it should
be moderate.

I finally had success in porting UNIX V7 to my ECO32 processor
which runs on an XESS XSA-3S1000 board. I put the board onto
an XST extender board, which gives me two serial interfaces
and an IDE connector for the hard disk (as well as a bunch of
other interfaces - audio, video, ethernet, USB - but I cannot
use them yet from within V7).

The board has 32 Mbytes of SDRAM. I used a slightly modified
version of the RAM controller that XESS is providing (thanks
to Dave van den Bout, who was always willing to help). The
memory is relatively slow, so the machine would benefit a lot
from a cache.

A port to the Digilent 3E Starter Board with its DDR RAM
is also on my agenda. But as always, there are many ideas
and little time to spare...

Hellwig

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--- In f...@yahoogroups.com, Hellwig Geisse wrote:
>
> Hi Richard,
>
> > As you may recall, I got the IBM 1130 emulation to run on that board
> > and since then I have also gotten a PDP11-xx to run. The xx would be
> > -40 if I had the MMU working. As it is, it runs RTL fairly well. I
> > want the -40 version so I can run Unix V6.
>
> very nice! If I remember correctly, the MMU of the -40 isn't
> that complicated, so that the effort of implementing it should
> be moderate.
>

There is a project http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html that has all the details for the PDP11-40.

The logic is written in another HDL named SFL. It's a wonderful language but, for whatever reason, when the provided VHDL translator converted the code, I couldn't get XST to accept it. There is also the problem familiar to all compiled code: the output is nearly unreadable. Hundreds of nets all similarly named with a numeric suffix.

I think I'll look at the PDP11-40 simulator and see how they did the MMU.

I got sidetracked again. My grandson has developed an interest in retro games. I have a Mame cabinet but he's into Nintendo, Atari and that stuff. So, I bought the Parallax Propeller game development board to show him around. I'm also messing with the FPGA arcade game.

I'll get back to the PDP-11 in a month or two. I first want to finish a multi-boot gadget that will allow me to reconfigure the S3SB to emulate the Z80-CP/M system, the IBM 1130 or the PDP11 based on a dipswitch setting. The physical hardware can all be common. They all need a disk drive (CF), seven segment displays, console switches and serial ports. Only the internals are different. In fact, a single 2GB CF will probably provide the full disk capacity of all the machines combined.

I am getting very familiar the *nix 'dd' command...

Richard

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On Fri, Oct 02, 2009 at 06:57:02PM -0000, rtstofer wrote:
> I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core.

If you have a relatively recent ISE you should be able to generate a
DDR interface using the memory interface generator (MIG). I believe it
is also included in the Webpack version. This is probably your best
bet. Getting the opencores DDR controller to work can be done but was
quite troublesome (at least for me).

/Andreas
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On Mon, 2009-10-05 at 13:04 +0000, rtstofer wrote:

> I got sidetracked again. My grandson has developed an interest in
> retro games. I have a Mame cabinet but he's into Nintendo, Atari and
> that stuff. So, I bought the Parallax Propeller game development board
> to show him around. I'm also messing with the FPGA arcade game.

My son developed a version of Tetris on top of the ECO32
computer system. He invented a special terminal for block
graphics, an audio generating circuit for the beeps, and
wrote the gaming logic in C. You can find some pictures,
the hardware description (Verilog) and the game code here:

http://vshg01.mni.fh-giessen.de/index.php?section=projects&subsection=tetris

The text is in German, I'm sorry. We use the game to show
an example of what we are doing in our department in order
to attract students.

Hellwig

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--- In f...@yahoogroups.com, Hellwig Geisse wrote:
>
> On Mon, 2009-10-05 at 13:04 +0000, rtstofer wrote:
>
> > I got sidetracked again. My grandson has developed an interest in
> > retro games. I have a Mame cabinet but he's into Nintendo, Atari and
> > that stuff. So, I bought the Parallax Propeller game development board
> > to show him around. I'm also messing with the FPGA arcade game.
>
> My son developed a version of Tetris on top of the ECO32
> computer system. He invented a special terminal for block
> graphics, an audio generating circuit for the beeps, and
> wrote the gaming logic in C. You can find some pictures,
> the hardware description (Verilog) and the game code here:
>
> http://vshg01.mni.fh-giessen.de/index.php?section=projects&subsection=tetris
>
> The text is in German, I'm sorry. We use the game to show
> an example of what we are doing in our department in order
> to attract students.
>
> Hellwig
>

Both projects are terrific! I may attempt to replicate them in the near future using the same board.

I am particularly interested in the SDRAM controller and the LCC port.

Thanks for posting the link!

Richard

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On Mon, 05 Oct 2009 13:04:44 -0000, you wrote:

>--- In f...@yahoogroups.com, Hellwig Geisse wrote:
>>
>> Hi Richard,
>>
>> > As you may recall, I got the IBM 1130 emulation to run on that board
>> > and since then I have also gotten a PDP11-xx to run. The xx would be
>> > -40 if I had the MMU working. As it is, it runs RTL fairly well. I
>> > want the -40 version so I can run Unix V6.
>>
>> very nice! If I remember correctly, the MMU of the -40 isn't
>> that complicated, so that the effort of implementing it should
>> be moderate.
>
>There is a project http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html that
>has all the details for the PDP11-40.
>
>The logic is written in another HDL named SFL. It's a wonderful
>language but, for whatever reason, when the provided VHDL translator
>converted the code, I couldn't get XST to accept it. There is also
>the problem familiar to all compiled code: the output is nearly
>unreadable. Hundreds of nets all similarly named with a numeric
>suffix.

Wasn't the link for a verilog translator? I assume XST accepts that
but the sfl2vl was noted as verilog, not VHDL, on that web page. Does
sfl2vl produce VHDL, as well?

>I think I'll look at the PDP11-40 simulator and see how they did the
>MMU.
>I'll get back to the PDP-11 in a month or two.
>

I'm wondering where one might come across an old PDP-11/45 or
PDP-11/70 front panel. The switch system, at the very least, would be
nice to have. Probably hard to come across, though.

Jon
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--- In f...@yahoogroups.com, Jon Kirwan wrote:

> Wasn't the link for a verilog translator? I assume XST accepts that
> but the sfl2vl was noted as verilog, not VHDL, on that web page. Does
> sfl2vl produce VHDL, as well?
When you install the entire package, you get sfl2vl and sfl2vh which are scripts that invoke sfl2vlbin.exe. sfl2vh adds a -vhdl option.

> I'm wondering where one might come across an old PDP-11/45 or
> PDP-11/70 front panel. The switch system, at the very least, would be
> nice to have. Probably hard to come across, though.
>
> Jon
>

It would be very nice to either buy such a panel or build something similar. That's one of the reasons I am looking at multi-boot for the FPGA. I could build a panel like the PDP11 or even one like the Altai 8800. Lots of switches and lights. It would work for just about any 16 bit core.

Looking at the ECO-32 core, I might want to rethink how that panel should look. I think I will give up on discrete LEDs and an octal LED layout probably doesn't make it either. Probably the best scheme is to use 8 digit 7 segment displays with one of the Maxim controller chips. I already use this chip for my 2 row 8 digit display.

Console switch entry seems workable in a 16 bit environment. It gets out of hand for a 32 bit machine. I suspect that a hex keypad would be a better solution.

Now, as the FPGA is controlling all this stuff, it would be possible for the PDP-11 core to define everything as octal and the other cores to define everything as hex.

The neatest solution I can come up with is a touch screen display. There is absolutely no reason that the register contents need to be presented in strictly real time. You can't see the lights blink anyway. I nice little touch screen would be perfect. Add a menu system so you can get to the 'keypad' and you're good to go.

Richard

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re: console switches

I think the primary purpose is in allowing examine-deposit and single stepping. Sure, there are some programs that get some switch settings but I haven't done that kind of thing since my 1130 days.

Even if I used an LCD for display, a keypad for entry and a few toggle switches, I could live with it.

In fact, using the LCD display allows the running core to decide what information to display and where to display it.

I suppose a monitor with a VGA terminal is the next 'upgrade' but that just doesn't make a nice front panel.

I need to spend more time thining about this. I hadn't thought I would be messing around with a 32 bit core so I haven't fully digested the ramifications.

Richard

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Sorry if this is duplicated - I seem to have
a problem with sending mail.

On Mon, 2009-10-05 at 11:16 -0700, Jon Kirwan wrote:

> I just don't like a keyboard and 7-seg display system. If I accepted
> that much, I'd probably go with the bootstrap rom and a serial port.
> That way I can use whatever I have handy and it doesn't take up much
> space, inherently, and I get to use real characters and not just what
> I'm stuck with regarding the 7-seg displays (not much, really.) Plus,
> I can add function, easily, without changing hardware.

ECO32 has exactly that: a bootstrap ROM (stored in
the Flash on the XESS board that also holds the
bitstring to initialize the FPGA) communicating to
a terminal (or a terminal emulation) over a serial
line. There are commands to read and alter register
contents as well as memory locations, set a breakpoint,
single-step instructions, run a program, boot from
the IDE disk, inspect and modify the TLB contents,
and other useful stuff for bringing up a new system.

Hellwig

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On Mon, 2009-10-05 at 11:16 -0700, Jon Kirwan wrote:

> I just don't like a keyboard and 7-seg display system. If I accepted
> that much, I'd probably go with the bootstrap rom and a serial port.
> That way I can use whatever I have handy and it doesn't take up much
> space, inherently, and I get to use real characters and not just what
> I'm stuck with regarding the 7-seg displays (not much, really.) Plus,
> I can add function, easily, without changing hardware.

ECO32 has exactly that: a bootstrap ROM (stored in
the Flash on the XESS board that also holds the
bitstring to initialize the FPGA) communicating to
a terminal (or a terminal emulation) over a serial
line. There are commands to read and alter register
contents as well as memory locations, set a breakpoint,
single-step instructions, run a program, boot from
the IDE disk, inspect and modify the TLB contents,
and other useful stuff for bringing up a new system.

Hellwig

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Jon, Richard, Hellwig, Andreas, and others,

You might like to check out Henk Gooijen's PDP-11 web site. I think he
might have been machining his own front panels ... I'm not 100% sure.

http://www.pdp-11.nl/

John.

Jon Kirwan wrote:
>
> I'm wondering where one might come across an old PDP-11/45 or
> PDP-11/70 front panel. The switch system, at the very least, would be
> nice to have. Probably hard to come across, though.
>
> Jon
>
>

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On Wed, 07 Oct 2009 00:15:10 +1100, you wrote:

>Jon, Richard, Hellwig, Andreas, and others,
>
>You might like to check out Henk Gooijen's PDP-11 web site. I think he
>might have been machining his own front panels ... I'm not 100% sure.
>
>http://www.pdp-11.nl/

Okay. Now I'm impressed I wonder if Henk would be interested in
adopting me! ;)

Jon
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--- On Sun, 10/4/09, John Kent wrote:
> > I was having a discussion with Tommy Thorn on this list back in April
> > this year about his MIPS compatible YARI CPU that used 4-way
> > associative instruction and data cache. That might give you some
> > design clues.
> >
> > http://yari.thorn.ws/YARI/Introduction.html
> >
> > I've seen very little activity on this list since then. I hope my
> > email address has been working.

Thanks for the pitch. I've been very busy since, but there are a few
changes in the "pipeline": SDRAM support for DE2-70 and SSRAM support
for ML-401.

There is definitely a lack of DDR controllers. This is truly a Frequently
Asked Question. A while back there was a posting of a port of an Open Cores DDR controller to one of the Digilent Spartan 3 boards. I got it
running on the Spartan 3S1600 board.

All modern dynamic RAM are designed for caches. The data cache and instruction cache in YARI should be fairly straight forward to follow, but they also aren't particularly sophisticated. In particular they:
- Use random replacement. There is a request for LRU replacement for real-
time reasons.
- Are write through caches. Implementing a write-back cache requires an
additional bitmap for dirty lines. (Also the line replacement policy
design space grows more interesting). I compensate partially by hac
- Waits for a full line before proceeding. Implementing critical word
first isn't complicated, but the extra tracking is likely to hurt
timing.

Tommy

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Tommy Thorn wrote:
> Thanks for the pitch. I've been very busy since, but there are a few
> changes in the "pipeline": SDRAM support for DE2-70 and SSRAM support
> for ML-401.
>
> There is definitely a lack of DDR controllers. This is truly a Frequently
> Asked Question. A while back there was a posting of a port of an Open Cores DDR controller to one of the Digilent Spartan 3 boards. I got it
> running on the Spartan 3S1600 board.
>
> All modern dynamic RAM are designed for caches. The data cache and instruction cache in YARI should be fairly straight forward to follow, but they also aren't particularly sophisticated. In particular they:
> - Use random replacement. There is a request for LRU replacement for real-
> time reasons.
> - Are write through caches. Implementing a write-back cache requires an
> additional bitmap for dirty lines. (Also the line replacement policy
> design space grows more interesting). I compensate partially by hac
> - Waits for a full line before proceeding. Implementing critical word
> first isn't complicated, but the extra tracking is likely to hurt
> timing.
>
> Tommy
>
Hi Tommy,

I saw the DE2-70 board on your web site. I hope to get to play with a
DE2-70 board shortly for some image processing applications. I've
downloaded a snap shot of your design files, so I might be able to try
it out soon.

Can you possible explain random replacement a little better and excuse
my ignorance, but what does LRU stand for ?

John.

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--- In f...@yahoogroups.com, John Kent wrote:
> Can you possible explain random replacement a little better and excuse
> my ignorance, but what does LRU stand for ?

What about :
http://en.wikipedia.org/wiki/Cache_algorithms

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--- On Thu, 10/8/09, e2kcpu wrote:

> From: e2kcpu
> Subject: [fpga-cpu] Re: Using DDR RAM
> To: f...@yahoogroups.com
> Date: Thursday, October 8, 2009, 5:45 AM
> --- In f...@yahoogroups.com,
> John Kent wrote:
> > Can you possible explain random replacement a little
> better and excuse
> > my ignorance, but what does LRU stand for ?
>
> What about :
> http://en.wikipedia.org/wiki/Cache_algorithms

That's technically accurate, but probably not meaningful without sufficient background.

John, I don't think I have enough time to do the topic justice. I strongly encourage you get the a copy of Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
Seriously, this should be considered required reading for anyone on this list.

Of course, my replacement is only /pseudo-/random as I use the low two bits of a 10-bit LFSR, not all that random actually.

Cheers
Tommy

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e2kcpu wrote:
> --- In f...@yahoogroups.com, John Kent wrote:
>
>> Can you possible explain random replacement a little better and excuse
>> my ignorance, but what does LRU stand for ?
>>
>
> What about :
> http://en.wikipedia.org/wiki/Cache_algorithms
>
>
Yep, Least Recently Used ...
Should have thought of that.

Thanks

John.

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Tommy Thorn wrote:
> --- On Thu, 10/8/09, e2kcpu wrote:
>
>
>> From: e2kcpu
>>
>>
>> What about :
>> http://en.wikipedia.org/wiki/Cache_algorithms
>>
>
> That's technically accurate, but probably not meaningful without sufficient background.
>
> John, I don't think I have enough time to do the topic justice. I strongly encourage you get the a copy of Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
> Seriously, this should be considered required reading for anyone on this list.
>
> Of course, my replacement is only /pseudo-/random as I use the low two bits of a 10-bit LFSR, not all that random actually.
>
> Cheers
> Tommy
>
Thanks Tommy,

My delay in responding is because I am working on a conference paper
that is over due, although developing effective caching techniques is an
important aspect of my research.

John.

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Tommy Thorn wrote:
> --- On Thu, 10/8/09, e2kcpu wrote:
>
> That's technically accurate, but probably not meaningful without sufficient background.
>
> John, I don't think I have enough time to do the topic justice. I strongly encourage you get the a copy of Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk
> Seriously, this should be considered required reading for anyone on this list.
>
> Of course, my replacement is only /pseudo-/random as I use the low two bits of a 10-bit LFSR, not all that random actually.
>
> Cheers
> Tommy
>
I have seen that book, although I think my local bookshop might have had
difficulty in getting it in. I did buy "The Art of Multiprocessor
Programming" by Herlihy and Shavit, although that covers more
concurrency and interlocks than caching.

John.

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The H&P is considered the "bible" of computer architecture. Amazon is your =
friend.
Tommy
--- On Fri, 10/9/09, John Kent wrote:

> From: John Kent
> Subject: Re: [fpga-cpu] Re: Using DDR RAM
> To: f...@yahoogroups.com
> Date: Friday, October 9, 2009, 10:58 PM
>=20
>=20
> Tommy Thorn wrote:
> > --- On Thu, 10/8/09, e2kcpu
> wrote:
> >
> > That's technically accurate, but probably not
> meaningful without sufficient background.
> >
> > John, I don't think I have enough time to do the topic
> justice. I strongly encourage you get the a copy of
> Patterson & Hennessey: http://www.amazon.com/Computer-Architecture-Quanti=
tative-Approach-4th/dp/0123704901/ref=3Ddp_ob_image_bk
> > Seriously, this should be considered required reading
> for anyone on this list.
> >
> > Of course, my replacement is only /pseudo-/random as I
> use the low two bits of a 10-bit LFSR, not all that random
> actually.
> >
> > Cheers
> > Tommy
> >=A0=A0=A0
> I have seen that book, although I think my local bookshop
> might have had=20
> difficulty in getting it in. I did buy "The Art of
> Multiprocessor=20
> Programming"=A0 by Herlihy and Shavit, although that
> covers more=20
> concurrency and interlocks than caching.
>=20
> John.
>=20
> --=20
> http://www.johnkent.com.au
> http://members.optusnet.com.au/jekent
>=20
>=20
>=20
> ------------------------------------
>=20
> To post a message, send it to: f...@yahoogroups.com
> To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups=
.comYahoo!
> Groups Links
>=20
>=20
> =A0 =A0 mailto:f...@yahoogroups.com
>=20
>=20
>=20
=20=20=20=20=20=20
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--- In f...@yahoogroups.com, Tommy Thorn wrote:
>
> The H&P is considered the "bible" of computer architecture. Amazon is your friend.
> Tommy

Ordered last week. Should be here soon.

Richard

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--- In f...@yahoogroups.com, "rtstofer" wrote:
>
> --- In f...@yahoogroups.com, Tommy Thorn wrote:
> >
> > The H&P is considered the "bible" of computer architecture. Amazon is your friend.
> >
> >
> > Tommy
>
> Ordered last week. Should be here soon.
>
> Richard
>

Is their a prep book for before "Computer Architecture: A Quantitative Approach"?

Norm

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On Thu, 2009-10-15 at 03:30 +0000, normnet2003 wrote:

> Is their a prep book for before "Computer Architecture: A Quantitative
> Approach"?

"Computer Organization & Design: The Hardware/Software Interface"
by the same pair of authors.

Hellwig

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--- In f...@yahoogroups.com, Hellwig Geisse wrote:
>
> On Thu, 2009-10-15 at 03:30 +0000, normnet2003 wrote:
>
> > Is their a prep book for before "Computer Architecture: A Quantitative
> > Approach"?
>
> "Computer Organization & Design: The Hardware/Software Interface"
> by the same pair of authors.
>
> Hellwig
>

If you want to do non-restoring division and you can't seem to 'get it' via the standard texts, there's a nice description in "Introduction To Arithmetic For Digital Systems Designes" by Waser and Flynn (1982). They even have a 'microcode' description that makes it pretty easy to implement in VHDL or Verilog.

I really wanted 2's complement non-restoring division. I bought a veritable library of books on computer arithmetic until I finally got the answer (that I could understand). Pretty expensive divider...

I buy a lot of used books at www.alibris.com And the rest at Amazon...

For a VERY introductory text, I like Computer Architecture (2d edition) by Foster ($3 at Alibris). The book is quite obsolete and talks about stuff like drum memory but there is a discussion of a very elementary computer (BLUE) that nobody would want to buy today. All of the gate level logic is shown and it was a kick to implement in a Spartan 3. Thirty years ago I was thinking about buildling it in TTL but the 8080 came out and I jumped in with the Altair 8800.

There is a table driven assembler ( http://home.comcast.net/~tasm/ ) which makes it trivial (maybe a couple of hours work) to implement a full featured cross-assembler for the processor.

I was thinking about BLUE as a learning exercise and science project for my grandson. In the early '60s you could have been king of the hill with a computer like this. OK, maybe late '50s.

Even the IBM1130 (released in 1965) was available with just 4k and paper tape. The 27 pass Fortran compiler worked just fine (AFAIK). BLUE has similar features but a much reduced instruction set.

Richard

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On Thu, 15 Oct 2009, rtstofer wrote:

>
8<--snip
>
> For a VERY introductory text, I like Computer Architecture (2d edition)
> by Foster ($3 at Alibris). The book is quite obsolete and talks about
> stuff like drum memory but there is a discussion of a very elementary
> computer (BLUE) that nobody would want to buy today. All of the gate
> level logic is shown and it was a kick to implement in a Spartan 3.
> Thirty years ago I was thinking about buildling it in TTL but the 8080
> came out and I jumped in with the Altair 8800.
>
Yes, this one is worth tracking down, it's a good introduction. BLUE also
bears more than a passing resemblance to the Apollo Guidance Computer.

Another introductory text which has some good examples is Carpinelli's
'Computer Systems Organization and Architecture' but it's not particularly
cheap, even second hand. The sections on arithmetic and cache are good
with RTL descriptions and schematics.

Also secondhand and possibly possibly worth a look is Feldman &
Retter's 1994 "Computer Architecture, A designer's text based on a generic
RISC" ($6)

Nigel G
--
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Department of Design & Engineering,
Bristol Institute of Technology , UWE, Bristol, BS16 1QY
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--- In f...@yahoogroups.com, Nigel.Gunton@... wrote:

> Yes, this one is worth tracking down, it's a good introduction. BLUE also
> bears more than a passing resemblance to the Apollo Guidance Computer.
>

I bought a CD on eBay that documents the AGC. There is at least one project on the Internet that implements a version of it but it's HUGE (physically).

I have been thinking about implementing a version in an FPGA. The problem is what to actually DO with it. It's not like I have a bunch of retro-rockets out in the garage. Still, it would be a good addition to the NASA Space Shuttle "Liftoff" CD/game.

The control panel is pretty easy. A few 7 segment displays and a keypad.
> Another introductory text which has some good examples is Carpinelli's
> 'Computer Systems Organization and Architecture' but it's not particularly
> cheap, even second hand. The sections on arithmetic and cache are good
> with RTL descriptions and schematics.

Alibris has copies from $25 I look forward to reading it!

>
> Also secondhand and possibly possibly worth a look is Feldman &
> Retter's 1994 "Computer Architecture, A designer's text based on a generic
> RISC" ($6)

Again, this is something I will enjoy reading.

I really appreciate all of the recommendations for my library but it's clearly gotten out of hand. I still have my original "8080 Microcomputer Systems User's Manual" from 1975. And everything in between... Some of the books are classics, others are just old. The problem is separating them.

Richard

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--- On Wed, 10/14/09, normnet2003 wrote:
> From: normnet2003
> Tommy Thorn wrote:
> > >
> > > The H&P is considered the "bible" of computer
> architecture. Amazon is your friend.
>
> Is their a prep book for before "Computer Architecture: A
> Quantitative Approach"?

I don't understand. The book I cited, http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk, _is_ "Computer Architecture: A Quantitative Approach".

One of the things that is appreciable about this book is that it's kept reasonable well up to date, though a lot of material from the 3rd ed was dropped in the 4th. I have both and look to both for coverage on topics.

A lot of other books have been mentioned in this thread. I'm sure they are fine too. I also have "classic" text and some that are merely "old", but for state of the art I haven't found anything better than the above.
What happened to the original topic, on DDR SDRAM controllers? So far the only I've heard of is the one from OpenCores.

Tommy

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--- In f...@yahoogroups.com, Tommy Thorn wrote:
>
> --- On Wed, 10/14/09, normnet2003 wrote:
> > From: normnet2003
> > Tommy Thorn wrote:
> > > >
> > > > The H&P is considered the "bible" of computer
> > architecture. Amazon is your friend.
> >
> > Is their a prep book for before "Computer Architecture: A
> > Quantitative Approach"?
>
> I don't understand. The book I cited, http://www.amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_image_bk, _is_ "Computer Architecture: A Quantitative Approach".
>
> One of the things that is appreciable about this book is that it's kept reasonable well up to date, though a lot of material from the 3rd ed was dropped in the 4th. I have both and look to both for coverage on topics.
>
> A lot of other books have been mentioned in this thread. I'm sure they are fine too. I also have "classic" text and some that are merely "old", but for state of the art I haven't found anything better than the above.
> What happened to the original topic, on DDR SDRAM controllers? So far the only I've heard of is the one from OpenCores.
>
> Tommy
>
I only asked because of several reviews like:
"This book has a lot of information, especially with the appendices on CD and in the back of the book. If you are new to Architecture, I wouldn't recommend it. Get a simpler book...maybe by the same authors, just the "prerequisite" for this one."

Norm

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Norm asked:
I only asked because of several reviews like:
"This book has a lot of information, especially with the appendices on CD
and in the back of the book. If you are new to Architecture, I wouldn't
recommend it. Get a simpler book...maybe by the same authors, just the
"prerequisite" for this one."
Norm

In the past I have also recommended Computer Organization by P&H e.g.
http://www.amazon.com/Computer-Organization-Design-Fourth-Architecture/dp/01
23744938 as a first book in computer architecture, particularly for
self-study. At least compared to CA:AQA, it offers a more gentle
introduction, e.g. to the details in the design of a pipelined RISC
processor.

Jan.

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Hi Tommy,

I don't really like using my Visa card on the internet. I'm always
worried about key loggers. I do run internet security software, but I'm
still worried about it.

I can get the book through the RMIT University Bookshop here in
Melbourne Australia, but I have a local bookshop that supports a number
of community activities that I am involved with, so I prefer to buy
books through them, even though they are a little more expensive. Buying
books from Amazon, you have to factor in exchange rates and postage,
which makes them a bit more expensive than the prices listed on the web.

The Least Recently Used algorithm is not hard to understand. I just
could not match up the letters in the acronym although I should have
thought about it before posting. I have done a paper design on a
associative cache using LRU some years ago. It used a shift register for
the address and a multiplexer which routed the address back to the head
of the FIFO every time a hit was detected. Cache addresses that fell out
the end of the shift register were written back to SDRAM if they were
dirty. As I think you mentioned, you needed to maintain a separate RAM
for each of the cache lines to flag if the cache has been written to.
Writing a flag to each individual word obviously does not help you
determine if the cache line is dirty. I also included a unique token for
each address in the associative cache to index the tag (?) cache. The
token is recycled if the cache entry is written back to memory.

John.

Tommy Thorn wrote:
> The H&P is considered the "bible" of computer architecture. Amazon is your friend.
> Tommy
>
>

--
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent

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With the australian dollar so strong right now, it has never been a
better time to buy from amazon.....

Brett Wildermoth BEng (ME) MPhil
Lecturer - Griffith School of Engineering
Email: B...@griffith.edu.au

On 18/10/2009, at 1:42 PM, John Kent wrote:

> Hi Tommy,
>
> I don't really like using my Visa card on the internet. I'm always
> worried about key loggers. I do run internet security software, but
> I'm
> still worried about it.
>
> I can get the book through the RMIT University Bookshop here in
> Melbourne Australia, but I have a local bookshop that supports a
> number
> of community activities that I am involved with, so I prefer to buy
> books through them, even though they are a little more expensive.
> Buying
> books from Amazon, you have to factor in exchange rates and postage,
> which makes them a bit more expensive than the prices listed on the
> web.
>
> The Least Recently Used algorithm is not hard to understand. I just
> could not match up the letters in the acronym although I should have
> thought about it before posting. I have done a paper design on a
> associative cache using LRU some years ago. It used a shift register
> for
> the address and a multiplexer which routed the address back to the
> head
> of the FIFO every time a hit was detected. Cache addresses that fell
> out
> the end of the shift register were written back to SDRAM if they were
> dirty. As I think you mentioned, you needed to maintain a separate RAM
> for each of the cache lines to flag if the cache has been written to.
> Writing a flag to each individual word obviously does not help you
> determine if the cache line is dirty. I also included a unique token
> for
> each address in the associative cache to index the tag (?) cache. The
> token is recycled if the cache entry is written back to memory.
>
> John.
>
> Tommy Thorn wrote:
> > The H&P is considered the "bible" of computer architecture. Amazon
> is your friend.
> >
> >
> > Tommy
> >
> > --
> http://www.johnkent.com.au
> http://members.optusnet.com.au/jekent
>

[Non-text portions of this message have been removed]

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Hi Brett,

Yes ... I was thinking of that when I wrote my post.

John.

Brett Wildermoth wrote:
> With the australian dollar so strong right now, it has never been a
> better time to buy from amazon.....
>
> Brett Wildermoth BEng (ME) MPhil
> Lecturer - Griffith School of Engineering
> Email: B...@griffith.edu.au
>
>

--
http://www.johnkent.com.au
http://members.optusnet.com.au/jekent

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--- In f...@yahoogroups.com, John Kent wrote:
>
> Hi Tommy,
>
> I don't really like using my Visa card on the internet. I'm always
> worried about key loggers. I do run internet security software, but I'm
> still worried about it.

Around here, our exposure to fraudulent transactions is limited to $50. Beyond that, the bank eats it (and passes it along...).

I use my Visa at least a couple of dozen times per month for online transactions and I have been doing it for as long as there have been online suppliers. I don't give it a moment's thought.

Richard

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