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Discussion Groups | FPGA-CPU | vliw code
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
vliw code - Bushra Qamar - Aug 11 4:54:40 2008
Hi
I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan
i was doing final year project on vliw
my project advisor said me to implement 8-bit risc
i did
then he said me to design 32 bit mips
i did
=A0
now he is not telling me what to do=20
he has gone to norway
and i have to submit my project on 16th of august
i couldnot understand what to do next and how:(
he did'nt tell us to do pipelining
now when i m reading j.fisher's book .so i got the idea that i shud know pi=
pelining and then trace schedling and then instruction level paralilsm
but how can i do all in 4 days???
do any one can help me???
=A0
=20=20=20=20=20=20
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I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan
i was doing final year project on vliw
my project advisor said me to implement 8-bit risc
i did
then he said me to design 32 bit mips
i did
=A0
now he is not telling me what to do=20
he has gone to norway
and i have to submit my project on 16th of august
i couldnot understand what to do next and how:(
he did'nt tell us to do pipelining
now when i m reading j.fisher's book .so i got the idea that i shud know pi=
pelining and then trace schedling and then instruction level paralilsm
but how can i do all in 4 days???
do any one can help me???
=A0
=20=20=20=20=20=20
[Non-text portions of this message have been removed]
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: vliw code - Malik Abdul Rehman - Aug 23 12:33:45 2008
Hey Bushi,
State some more details about your implementation.
What environment did you implement it in?
Some details about your datapath which you want to split?
You need to make sure there are no control or structural hazards in your
implementation. Instructions' dependency on previous instructions.
Ah! It's a bit too wide an ocean to jump in right now. State some more
details and may be you can get some help.
Cheers
All the best
/Malik
On Mon, Aug 11, 2008 at 10:54 AM, Bushra Qamarwrote:
> Hi
> I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan
> i was doing final year project on vliw
> my project advisor said me to implement 8-bit risc
> i did
> then he said me to design 32 bit mips
> i did
>
> now he is not telling me what to do
> he has gone to norway
> and i have to submit my project on 16th of august
> i couldnot understand what to do next and how:(
> he did'nt tell us to do pipelining
> now when i m reading j.fisher's book .so i got the idea that i shud know
> pipelining and then trace schedling and then instruction level paralilsm
> but how can i do all in 4 days???
> do any one can help me???
> [Non-text portions of this message have been removed]
>
>
>
[Non-text portions of this message have been removed]
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
State some more details about your implementation.
What environment did you implement it in?
Some details about your datapath which you want to split?
You need to make sure there are no control or structural hazards in your
implementation. Instructions' dependency on previous instructions.
Ah! It's a bit too wide an ocean to jump in right now. State some more
details and may be you can get some help.
Cheers
All the best
/Malik
On Mon, Aug 11, 2008 at 10:54 AM, Bushra Qamar
> Hi
> I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan
> i was doing final year project on vliw
> my project advisor said me to implement 8-bit risc
> i did
> then he said me to design 32 bit mips
> i did
>
> now he is not telling me what to do
> he has gone to norway
> and i have to submit my project on 16th of august
> i couldnot understand what to do next and how:(
> he did'nt tell us to do pipelining
> now when i m reading j.fisher's book .so i got the idea that i shud know
> pipelining and then trace schedling and then instruction level paralilsm
> but how can i do all in 4 days???
> do any one can help me???
> [Non-text portions of this message have been removed]
>
>
>
[Non-text portions of this message have been removed]
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )