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Discussion Groups | FPGA-CPU | Re: Max CPU speed
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Re: Max CPU speed - Tommy Thorn - Apr 1 23:23:22 2008
--- Rob Finch wrote:
> With 8MB/s of main memory bandwidth,
> What's a reasonable expectation for how fast a CPU
> may operate ?
>
> eg. 80 MHz ?
main memory bandwidth is orthogonal
to the CPU clock speed, assuming you're using
caches. You'll need an instruction cache at the
least, otherwise why bother talking about
performance.
If you're tied to an existing ISA, you'll find
yourself
fairly constrained. My MIPS implementation
(http://repo.or.cz/w/yari.git) currents gets about
55 MHz in a Cyclone EP1C20, lowest speed grade.
Experiments I did suggests that 90 MHz is feasible
with some rework (it's pending).
Ultimately you can't go faster than your register file
and caches will allow. In my experience, the
theoretical Fmax of the memory blocks is about twice
of what you can _actually_ get when you put several
of them together. Most of the loss is in routing
sadly.
Tommy
>
> Nexys board default config has about 20MB/s
> available; but I'm
> planning on using 12 MB/s to support a display.
>
> RF
> ------------------------------------
>
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> f...@yahoogroups.com
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> Links
>
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> With 8MB/s of main memory bandwidth,
> What's a reasonable expectation for how fast a CPU
> may operate ?
>
> eg. 80 MHz ?
main memory bandwidth is orthogonal
to the CPU clock speed, assuming you're using
caches. You'll need an instruction cache at the
least, otherwise why bother talking about
performance.
If you're tied to an existing ISA, you'll find
yourself
fairly constrained. My MIPS implementation
(http://repo.or.cz/w/yari.git) currents gets about
55 MHz in a Cyclone EP1C20, lowest speed grade.
Experiments I did suggests that 90 MHz is feasible
with some rework (it's pending).
Ultimately you can't go faster than your register file
and caches will allow. In my experience, the
theoretical Fmax of the memory blocks is about twice
of what you can _actually_ get when you put several
of them together. Most of the loss is in routing
sadly.
Tommy
>
> Nexys board default config has about 20MB/s
> available; but I'm
> planning on using 12 MB/s to support a display.
>
> RF
> ------------------------------------
>
> To post a message, send it to:
> f...@yahoogroups.com
> To unsubscribe, send a blank message to:
> f...@yahoogroups.comYahoo! Groups
> Links
>
____________________________________________________________________________________
Like movies? Here's a limited-time offer: Blockbuster Total Access for one month at no cost.
http://tc.deals.yahoo.com/tc/blockbuster/text4.com
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )