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Discussion Groups | FPGA-CPU | Case statement accelerations

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Case statement accelerations - Rob Finch - Jan 18 19:19:25 2008

Just came across this (compiled code for processing switch statements)

// compare case value 1
// jump if eq
// compare case value 2
// jump if eq
// compare case value 3
// jump if eq
// compare case value 4
// jump if eq
// ...
//

What if there a lot of cases ?

There's got to be a better way. Something like:

// rep: cmpswne ; repeat compare consecutive words for equality
// jmp adrtbl[reg] ; jump when a match occurs

OR

rep: cmpswAndJmp
RTF

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Re: Case statement accelerations - Veronica Merryfield - Jan 18 21:23:53 2008

Having investigated some while ago, what a number of compilers do with switches, it looked like most compilers mix jump tables and single jumps based on how many consecutive entries there are, number of groups and how sparse some entries are. It seems the compilers looked at moved to jump tables at about or 6 entries depending on speed and size optimisation directives.

If you have never done this with a good compiler, such as gcc, it is worth doing to witness what the code generators will do with switches.
----- Original Message -----
From: Eric Smith
To: f...@yahoogroups.com
Sent: Friday, January 18, 2008 4:07 PM
Subject: Re: [fpga-cpu] Case statement accelerations
Rob wrote:
> Just came across this (compiled code for processing switch statements)
> // compare case value 1
> // jump if eq
> // compare case value 2
> // jump if eq

Yes, in fact many compilers will generate jump tables if the case values
are in a consecutive or mostly-consecutive range. Some compilers have
options or pragmas to allow control of that feature.

[Non-text portions of this message have been removed]

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