Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | Decoding during EX (execution) stage (ALU)
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Decoding during EX (execution) stage (ALU) - Rob Finch - Jul 29 17:06:24 2007
Somewhat related is decoding during the EX stage (late stage
decoding).
Lately I've been switching to providing more decoding during the EX
stage and moving it out of the usual decode stage. The FPGA's seem to
be good enough at decoding, that there is typically only a minimal
slowdown. I've found it a lot easier to pass a signal called 'opcode'
around rather than a whole bunch of decodes.
If it's an invalid opcode the output is set to zero so that the
outputs of different units can just be or'd together.
`define XORL 7'd16
`define ANDL 7'd17
`define ORL 7'd18
`define XORM 7'd20
`define ANDM 7'd21
`define ORM 7'd22
`define XORH 7'd24
`define ANDH 7'd25
`define ORH 7'd26
module logic_unit(op, a, b, o);
parameter WID = 64;
input [6:0] op; // opcode
input [WID:1] a; // operand 'a'
input [WID:1] b; // operand 'b'
output [WID:1] o; // output result
reg [WID:1] o;
always @(a or b or op)
case (op)
`XORL,
`XORM,
`XORH: o = a ^ b;
`ANDL,
`ANDM,
`ANDH: o = a & b;
`ORL,
`ORM,
`ORH: o = a | b;
default: o = {WID{1'b0}};
endcase
endmodule
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
decoding).
Lately I've been switching to providing more decoding during the EX
stage and moving it out of the usual decode stage. The FPGA's seem to
be good enough at decoding, that there is typically only a minimal
slowdown. I've found it a lot easier to pass a signal called 'opcode'
around rather than a whole bunch of decodes.
If it's an invalid opcode the output is set to zero so that the
outputs of different units can just be or'd together.
`define XORL 7'd16
`define ANDL 7'd17
`define ORL 7'd18
`define XORM 7'd20
`define ANDM 7'd21
`define ORM 7'd22
`define XORH 7'd24
`define ANDH 7'd25
`define ORH 7'd26
module logic_unit(op, a, b, o);
parameter WID = 64;
input [6:0] op; // opcode
input [WID:1] a; // operand 'a'
input [WID:1] b; // operand 'b'
output [WID:1] o; // output result
reg [WID:1] o;
always @(a or b or op)
case (op)
`XORL,
`XORM,
`XORH: o = a ^ b;
`ANDL,
`ANDM,
`ANDH: o = a & b;
`ORL,
`ORM,
`ORH: o = a | b;
default: o = {WID{1'b0}};
endcase
endmodule
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Decoding during EX (execution) stage (ALU) - Tommy Thorn - Jul 29 19:28:53 2007
Rob Finch wrote: Somewhat related is decoding during the EX stage
(late stage
decoding).
Lately I've been switching to providing more decoding during the EX stage and moving it out of the usual decode stage. The FPGA's seem to be good enough at decoding, that there is typically only a minimal slowdown. I've found it a lot easier to pass a signal called 'opcode' around rather than a whole bunch of decodes.
Quartus II, and probably ISE too, will re-time those decodes if you let them, effectively do the work for you.
On a related note, I find it hard to get consistent results when hard tweaking designs. It seems Quartus does practically as good a job when the logic is straight forward, as long as it has enough pipeline stages to spread the logic over. Only when I go to the extreme of hand instantiating logic does things stay consistent, but it's hard to be productive that way.
Regards,
Tommy
---------------------------------
Boardwalk for $500? In 2007? Ha!
Play Monopoly Here and Now (it's updated for today's economy) at Yahoo! Games.
[Non-text portions of this message have been removed]
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
decoding).
Lately I've been switching to providing more decoding during the EX stage and moving it out of the usual decode stage. The FPGA's seem to be good enough at decoding, that there is typically only a minimal slowdown. I've found it a lot easier to pass a signal called 'opcode' around rather than a whole bunch of decodes.
Quartus II, and probably ISE too, will re-time those decodes if you let them, effectively do the work for you.
On a related note, I find it hard to get consistent results when hard tweaking designs. It seems Quartus does practically as good a job when the logic is straight forward, as long as it has enough pipeline stages to spread the logic over. Only when I go to the extreme of hand instantiating logic does things stay consistent, but it's hard to be productive that way.
Regards,
Tommy
---------------------------------
Boardwalk for $500? In 2007? Ha!
Play Monopoly Here and Now (it's updated for today's economy) at Yahoo! Games.
[Non-text portions of this message have been removed]
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )