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Discussion Groups | FPGA-CPU | Polled interrupts - Barrel Processor
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Polled interrupts - Barrel Processor - Rob Finch - Nov 17 6:41:56 2006
A barrel processor seems like a natural when the PLD has the ability
to support multi-contexts. All of those "extra" registers are already
just sitting there idle.
It's very tempting to use polled interrupts when a lot of context is
available. The cpu could switch to an interrupt context every few
clock cycles.
The context indexing in a barrel processor doesn't have to happen in
a linear fashion. I have the index controlled by a loadable circular
shift register in one design (32 entry, four bits wide). So it can be
controlled which context is active during any cycle.
Of course there are some restrictions on the context order.
With a multi-core cpu, one core could be dedicated to polled
interrupt handling.
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to support multi-contexts. All of those "extra" registers are already
just sitting there idle.
It's very tempting to use polled interrupts when a lot of context is
available. The cpu could switch to an interrupt context every few
clock cycles.
The context indexing in a barrel processor doesn't have to happen in
a linear fashion. I have the index controlled by a loadable circular
shift register in one design (32 entry, four bits wide). So it can be
controlled which context is active during any cycle.
Of course there are some restrictions on the context order.
With a multi-core cpu, one core could be dedicated to polled
interrupt handling.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Polled interrupts - Barrel Processor - Eric Smith - Nov 17 17:18:51 2006
Rob wrote:
> The context indexing in a barrel processor doesn't have to happen in
> a linear fashion. I have the index controlled by a loadable circular
> shift register in one design (32 entry, four bits wide). So it can be
> controlled which context is active during any cycle.
>
> Of course there are some restrictions on the context order.
There don't *have* to be restrictions on the context order. However,
if you do impose restrictions, such that no thread is allowed to
execute more frequently than the pipleline depth, you can avoid
the need for register forwarding.
Eric
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> The context indexing in a barrel processor doesn't have to happen in
> a linear fashion. I have the index controlled by a loadable circular
> shift register in one design (32 entry, four bits wide). So it can be
> controlled which context is active during any cycle.
>
> Of course there are some restrictions on the context order.
There don't *have* to be restrictions on the context order. However,
if you do impose restrictions, such that no thread is allowed to
execute more frequently than the pipleline depth, you can avoid
the need for register forwarding.
Eric
______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )