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Discussion Groups | FPGA-CPU | Question to ChipScope Pro users
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Question to ChipScope Pro users - Jae Young Hur - Aug 17 3:16:00 2005
Hi
I need some comment from ChipScope Pro users, as I am new to ChipScope Pro VIO. I am using Xilinx ISE 6.3.
Timing simulation after PAR (post place and route) simulation is okay. I exercised simple counter with ILA coregenerator. It works fine. Problem is the VIO.
In ILA, proper behavior of the output signal can be seen. That is, the output signal behaves "0 -> 1 -> 2 -> 3 -> 4 -> ........."
But, in VIO console, output signal behaves "0 -> 3 -> 11 -> ..." (as an example), which is unexpected.
It seems that the problem is the "clock timing constraint".
My question is that
- Should the timing constraint (in UCF file) be different between the timing simulation and ChipScope Pro (VIO) ?
- If yes, what kind of constraint should be considered in order to make VIO work?. My UCF file, only clock period is constrained.
If someone has an (simple) working example of VIO, it will be nice to have some comments, how to shoot this trouble.
Thankyou in advance
__________________________________________________
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[Non-text portions of this message have been removed]
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
I need some comment from ChipScope Pro users, as I am new to ChipScope Pro VIO. I am using Xilinx ISE 6.3.
Timing simulation after PAR (post place and route) simulation is okay. I exercised simple counter with ILA coregenerator. It works fine. Problem is the VIO.
In ILA, proper behavior of the output signal can be seen. That is, the output signal behaves "0 -> 1 -> 2 -> 3 -> 4 -> ........."
But, in VIO console, output signal behaves "0 -> 3 -> 11 -> ..." (as an example), which is unexpected.
It seems that the problem is the "clock timing constraint".
My question is that
- Should the timing constraint (in UCF file) be different between the timing simulation and ChipScope Pro (VIO) ?
- If yes, what kind of constraint should be considered in order to make VIO work?. My UCF file, only clock period is constrained.
If someone has an (simple) working example of VIO, it will be nice to have some comments, how to shoot this trouble.
Thankyou in advance
__________________________________________________
">http://mail.yahoo.com
[Non-text portions of this message have been removed]
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )