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Discussion Groups | FPGA-CPU | (No subject)
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
(No subject) - Author Unknown - Apr 5 9:36:00 2005
>
> There was a paper about Hydra in last years FPL conference. I think they
> had an architecture with a processing element per square.
> But apparently a lot of their know-how is an efficient partitioning
> between smart high level algorithms running in software and parallel
> brute force search running in dozens of FPGAs.
>
A short note on this: They are using one FPGA per PC-node (but several
PCs). If someone is more interested in Hydra, I can provide the contact
to the 'chess-brain' behind it (as I'm in contact with this guy who is
also Autrian).
Martin
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> There was a paper about Hydra in last years FPL conference. I think they
> had an architecture with a processing element per square.
> But apparently a lot of their know-how is an efficient partitioning
> between smart high level algorithms running in software and parallel
> brute force search running in dozens of FPGAs.
>
A short note on this: They are using one FPGA per PC-node (but several
PCs). If someone is more interested in Hydra, I can provide the contact
to the 'chess-brain' behind it (as I'm in contact with this guy who is
also Autrian).
Martin
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )