xsoc-beta-092.zip dropped to www.fpgacpu.org/xsoc | FPGA-CPU

Welcome, new subscribers. We are now 17. I have just uploaded beta 0.92 to the web site. This includes a fix for issue #13, reported by Mike Butts, that the beta 0.90 xsoc-10xl-13.bit FPGA configuration was not working on his XS40+ v1.4 board (with 128 KB of RAM). (Why it worked for me, but not for him, is a long story. See the issues list if you are curious.) To effect the fix, I changed the XSOC.sch top-level schematic to drive XA<15> and XA16 (the 2 msbs of the v1.4+ board's 128 KB SRAM). XA16 is tied to GND for now. The various UCF constraint files were changed so that XA<15> and XA16 are tied to unbonded pins (and optimized away) for XS40 boards versions 1.2 and 1.3. On XS40 v1.4 and XS40+ v1.4 boards, XA<15>=P28 and XA16=P16. This is benign on the non-+ board and correctly drives the SRAM's A<16:15> on the XS40+ board. I refer you to the schematics on the last two pages of the XS40 board manual, http://www.xess.com/xs40-manual-v1_4.pdf. *** If you have an XS40+ v1.4, you need this fix, and you *want* this fix, because with it you will 'enjoy' almost 64 KB of external RAM. *** [I had to go to the trouble of differentiating the v1.2 and v1.3 boards from the v1.4 and v1.4+ boards, because in v1.3 and earlier, the FPGA pin P16 is also driven by inverter U3C. If we were to drive XA16 on P16 on one of these earlier boards, output contention could occur, and the FPGA or board could be damaged (or worse). I have added a strong warning to this effect in the Getting Started Guide.] Build 0.92 also corrects documentation problems reported by Messrs. Butts, Crowl, Sanchez, and Freidin, (thanks folks), removes encryption from the Acrobat docs, and now includes doc/xsoc-talk.pdf, an Acrobat representation of the transparencies of a talk on XSOC that I presented at the University of Waterloo in December. (This information is now also available on the web site at www.fpgacpu.org/xsoc/talk.pdf) Please keep that feedback, good or bad, coming. Looking ahead, with no pressing issues, I'm going to return to work on the Verilog version of XSOC/xr16 with the goal of adding that to the beta distribution as soon as possible. Once we have an adequate Verilog version, it should become the golden design representation. Development will likely proceed much more quickly and fixes and enhancements will be easier to share. At that point, as far as I am concerned, the schematic version can slowly fade away. (Also, I note that Mr. Sanchez has also indicated an interest in reimplementing the Verilog in VHDL.) But more on that later. From our News Desk, we note that VAutomation, provider of several synthesizable processor and peripheral cores aimed at ASIC prototyping in FPGAs, has been acquired by ARC Cores. See http://www.eet.com/story/OEG20000321S0015. "Market validation", as they say. Cheers, Jan Gray Gray Research LLC Visiting Waterloo, Ont., Canada.

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Discussion Groups | FPGA-CPU | xsoc-beta-092.zip dropped to www.fpgacpu.org/xsoc

xsoc-beta-092.zip dropped to www.fpgacpu.org/xsoc - Jan Gray, Gray Research LLC - Mar 22 1:14:00 2000