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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "isa"
Re: Max CPU speed
Tommy Thorn - Apr 1 2008
--- Rob Finch wrote:
> With 8MB/s of main memory bandwidth,
> What's a reasonable expectation for how fast a CPU
> may operate ?
>
> eg. 80 MHz ?
main memory ban... 
Unable to generate NIOS II
syyang85 - Mar 5 2008
Hi all,
I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3
development board from Altera.
I'm opening the example of Nios II system made by Altera.
But i ge... Re: Re: POP-11 (PDP-11/40 in an FPGA) [3 Articles]
Kolja Sulimma - Aug 22 2007
That should be an FAQ.
The bottom line:
- ISAs not protected at all
- Implementations covered by copyright. So do not use the original
schematics as a basis for your design.
... Re: 8-bit microprocessor
Hellwig Geisse - Mar 18 2007
On Mon, 2007-03-05 at 13:04 +0000, ashfaq_bse wrote:
> i m going to make a degree project of "8-bit microprocessor
> based on MIPS architecture (RISC) implemented on verilo... transputer fpga
Alex Gibson - Apr 5 2005
Spotted this in comp.arch.transputer and in comp.arch.fpga
by johnjakson JJ dated 02/04/2005 (yes 2nd of April)
Announcement
This first partial release date was chos... Re: Use for 2 bit opcode ? [3 Articles]
Kolja Sulimma - Apr 2 2005
Rob Finch wrote:
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, bu... Re: Re: why FPGA?
Kathy Quinlan - Jan 14 2005
OK in this thread, I am lost and wondering if I want to use an FPGA to
get data into and out of a PCI bus, how do I do it ? What are the
recomended ways ?
I do... Re: why FPGA?
- Jan 10 2005
--- In , Kolja Sulimma Re: Xilinx vs Altera / Microblaze vs Nios??? [3 Articles]
Göran Bilski - Dec 15 2004
Hi,
The custom function is attaching a full function on the FSL (fifo)
channels that MicroBlaze has.
Custom instruction has the drawback that you can only ... Re: Stack Machine Instruction Set [4 Articles]
Jan Gray - Nov 25 2004
Both relative call and absolute call take you from a fixed address to
another fixed address. So you don't need both.
Relative call might be smaller.
Relative cal... Re: Re: Simple Character CRT Core Needed
Arius - Rick Collins - Aug 31 2004
At 02:32 PM 8/31/2004, you wrote:
>I had seen the listing at opencores and it seemed far too complex.
>At the moment I think I just want 80x25 but it also nee... Processor selection [2 Articles]
Avinash Shetty - Jul 18 2003
Hi
Can any one let me know if there is any free open core for a 16 bit processor .
I have studied the Picoblaze ....but its just 8 bits and the Microblaze is 3... Java processor / RISC cpu
Martin Schoeberl - Mar 18 2003
Hi Josh,
an answer on the list again. I don't think it's off-topic and we don't annoy
anybody. This Java Processor _is_ a fpga cpu. So why not discuss it here? ... Re: Standalone system
Tommy Thorn - Jan 30 2003
Frank Kujawski wrote:
> Being new to this area, I have no idea where to start, so I am asking
> here:
> I would like to prototype a CPU design that I have thought... GNU lightning
Brian Davis - Jan 14 2003
Here's a link to an interesting virtual CPU:
http://www.gnu.org/software/lightning/
Provides a code library for dynamic code generation
targeting a v... Ann: ALTERA prototyping board
Martin Schoeberl - Oct 27 2002
As there are so many boards for the Xilinx family I would like to support the Altera users.
The board contains everything needed for cpu designs:
ACEX 1K50 FPGA ... RE: C runtime library for xr16 [2 Articles]
Jan Gray - Sep 9 2002
> From: Jeff Chang [mailto:]
> Hi all,
>
> Where can I find the complete c runtime library for
> xr16?
>
> Thanks,
> Jeff
Alas, that does not exis... Bus Arbitation [3 Articles]
Sumeet Suri - Apr 16 2002
HI guys,
I am looking to implement a Bus Arbiter in VHdl for my design. Right now
I have just 8 hosts (or devices) who request access for the Bus.
Each of the... 1 Billion transitors [2 Articles]
Ben Franchuk - Apr 1 2002
That sounds impressive, 1,000,000,0000 transistors. ( 10 Billion
marketing gates :) ). Did you know the PDP-8/S had 1001 transistors in
marketed in 1968?
Now wit... floorplanning ... can someone offer guru advice ?
Sean - Mar 23 2002
I'd like to practice floor planning and working with Xilinx tools so I grabbed
http://doc.union.edu/237/Projects/Mips/Vhdl/
an 8 bit constrained mips ... RE: hardware cpu scheduler, pointers to papers? [7 Articles]
Jan Gray - Mar 22 2002
XYRON
> I just saw a reference to a company in Washington state that
> sells an ip core that has a hardware scheduler.
That would be Xyron Semi of Vancouve... Re: VLIW processors anyone ? [2 Articles]
rtfinch35 - Mar 11 2002
>
> The challenging part of a VLIW project is the compiler. Unless
you're a
> glutton for tricky assembly programming, or have a very small and
> specific pro... Re: Re: Need debugging suggestions [2 Articles]
Ben Franchuk - Jan 29 2002
rtfinch35 wrote:
>> It depends what you mean by "design". I wrote the Verilog source for
> the processor completely from scratch, in that sense it is truely
> ori... NANO instruction set architecture [4 Articles]
Reinoud - Jan 16 2002
Hi all,
I've made an attempt at designing an efficient architecture for very
small implementations. The point of the architecture is the
combination of smal... Re: Bird Brained Idea (humour)
browsasaurus - Jan 5 2002
--- In fpga-cpu@y..., "rtfinch35" CISCifying RISC calls and returns [2 Articles]
- Nov 16 2001
(Rob babbling away again...)
In the perpetual analysis for, and in striving for the perfect isa,
it seems to me that cisc style calls and returns would be bette... Re: CPU Architectural Question [2 Articles]
Josh Fryman - Jul 29 2001
> No 3 factors that slowed CISC's down.
> 1) instruction sets geared to save memory
debatable, but i'll certainly accept it was a factor. #1 is
what i'd question.... Revamped Sparrow ISA [3 Articles]
- Jul 21 2001
I've revamped the ISA for a 32 bit version of the Sparrow core. If
anyone's interested take a look at
http://www.birdcomputer.ca/is_toc.html
Probably the mo... xr16vx in JHDL: v1.01
Mike Butts - Jul 3 2001
I've moved xr16vx up to rev 1.01. No changes to the source code.
I've fixed some doc errors, like the ones you found (thanks!),
and revised the xr16 ISA statements ... xr16vx in JHDL is running on chip
Mike Butts - Jun 10 2001
I have my implementation of xr16 in JHDL running reliably on
my Insight XC2S100 board. It's running a C program which is
echoing serial in to serial out, and also t... bit twiddling ISA's [3 Articles]
- Jun 10 2001
I seem to be at a bit of an impasse in my latest cpu design. Result
forwarding logic is limiting the clock speed to 57MHz (SpartanII-5
before floorplanning). I ca... Then I thought, a lot of work in one instruction [2 Articles]
- May 28 2001
The SpartanII 2S200 is soooo big (and yet so small). I'm
experimenting with additional ISA features in a 32 bit design.
I started thinking about the value of loop ... Register width [2 Articles]
- May 17 2001
Reality check: the primary purpose for supporting "wide" register
widths in a processor is to accommodate the addressing capability of
the processor (for pointers... RE: Multiplying, MicroBlaze
Jan Gray - Apr 10 2001
> Wow, that Microblaze looks impressive. But I wonder how realisitic
> the architecture is and what got "scrapped". 800 LUTs is amazing. I
> wonder how fast the xr1... Re: raw speed and benchmarks [4 Articles]
Mike Butts - Apr 9 2001
I'd say for sure the main reason MicroBlaze runs 125 MHz is
******** Pipelining **********
The MicroBlaze ISA must allow for lots and lots of pipeline stages....