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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "ide"
vliw code
Bushra Qamar - Aug 11 2008
Hi
I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan
i was doing final year project on vliw
my project advisor said me to implement 8-bit risc
i did
then he ... 
Small CPUs in FPGAs [19 Articles]
Rick Collins - Jul 31 2008
Hi,
It looks like this group has been slumbering for a bit. This seems to
be the ideal place to have my discussion, but I'm not sure if there
will be anyone listening? I se... SD card interface using FPGA [2 Articles]
k7ar...@gmail.com - Apr 22 2008
hai all , i am arun . i am working on interfacing SD card using FPGA. i am using SPI mode of communication to SD card .
1. i wrote the code in verilog for the identification mode ... Re: interconnection between FPGA and PC
rtstofer - Mar 10 2008
--- In f...@yahoogroups.com, "artiedc" wrote:
>
> --- In f...@yahoogroups.com, "RANJITH KUMAR REDDY"
> wrote:
> >
> > Hello
> >
> > Can any one help m... DWT in vhdl [4 Articles]
siva...@gmail.com - Feb 4 2008
hi,
how to implement discrete wavelet transform for image compression in vhdl.plz. give me brief idea. if anyone has source code please send to me.
thank you
To post ... Re: Re: Frame Grabber using FPGA thru webcam [3 Articles]
John Kent - Dec 27 2007
Hi Richard,
Yeah. My understanding is that he wants to do optical flow calculations.
This involves capturing two frames or a sequence of frames, dividing the
original image in... Re: Inferred Priority Encoder In VHDL
Tommy Thorn - Nov 28 2007
You could do worse than check out
http://www.cs.tut.fi/soc/Metzgen04.pdf
Even though it's an Altera perspective, the general
principles holds true for Xilinx as well.
> Is ... use C++ int__64 type variables in NIOS IDE [2 Articles]
paria354 - Nov 6 2007
does anyone know how to use C++ int__64 type variables when we want to
implement it on NIOS IDE?
coz IDE doesn't support upper than 32 bit integers.how can we use them
in a bi... Re: Hirose FX2 Backplane ? [4 Articles]
Leslie - Oct 20 2007
--- In f...@yahoogroups.com, "Rob Finch" wrote:
>
> Is there a Hirose FX2 100 pin backplane or cabling available ?
>
> I'd like to connect some Nexys boards together.
... FPGA routing - was - RE: Re: POP-11 (PDP-11/40 in an FPGA)
rtstofer - Oct 17 2007
> Why does everybody assume Xilinx is the *only* brand of FPGA's. I used
> Altera 10K.
I certainly prefer the licensing terms for WebPACK ISE over the Altera
equivalent. ... POP-11 (PDP-11/40 in an FPGA) [26 Articles]
Scott - Aug 16 2007
Hello,
I came across this old posting for the POP-11, but the original
URL no longer works. I'd really like to get the
VHDL source code for the POP-11 project if possible.
Ca... Re: Re: Microblaze In FPGA Virtex4 ML401? [2 Articles]
Tommy Thorn - Jul 26 2007
[Appologies if the formatting is missing or screwed up. Yahoo! Mail doessn't like me much.]
Martin Schoeberl wrote:Plasma was about 40 MHz in a Cyclone 1C12. However, the mai... Re: exclusive access RAM [4 Articles]
Eric Smith - Feb 11 2007
Rob wrote:
> Why not put the 'code' block in the 'RAM' block ? Then use a hardware
> guard, rather than using mutexes and semaphores.
Interesting idea, but I don't think it'... Re: Re: Multi-context processor [2 Articles]
Tobias Gogolin - Nov 9 2006
Does he say he has that?
Or is he proposing?
Its sounds relatively abstract
but if he already implemented that - he's all made...
My idea is more along the programmers model ... Re: Have NIOS and Microblaze killed off the fpga-cpu
John Kent - Aug 4 2006
Hi Hellwig,
H...@mni.fh-giessen.de wrote:
>
>
> > I've used a single phase clock on my designs. One clock cycle = one
> > instruction cycle.
>
> That's reall... Re: Wishbone comments - SimpCon [2 Articles]
Richard John - Nov 25 2005
I have used Chronology's TimingDesigner for drawing timing diagram.
This tool allowed me to not only draw timing diagram but also analyze and budget the entire path include... Re: Wishbone comments [4 Articles]
Martin Schoeberl - Nov 24 2005
> You are probably right for high clock rate interconnects or high latency
> accesses (DRAM, etc).
> However, WB works very well for single cycle accesses as you usually
>... System09 updates [2 Articles]
John Kent - Sep 18 2005
Just a notice to anyone playing with the System09 VHDL core,
There are a few updates to the CPU09 core.
JSR [0,S] did not work properly
The stack pointer was pre-dec... help req: poster session of my cpu
Umair siddiqui - Sep 13 2005
poster session is just another requirement of
university. since fpga related work was not completed,
i have to mainly present the simulation results.
ofcourse i'll pasting... Re: RAM loading via JTAG [5 Articles]
Piotr Zbysinski - EP\\H\\ - Aug 18 2005
----- Original Message -----
From: Richard Duits
To: lpc2000@lpc2...
Sent: Thursday, August 18, 2005 1:15 AM
Subject: Re: [lpc2000] RAM loading via JTAG
Wh... about fpga-cpu (recurring message)
Jan Gray - Aug 1 2005
I wish to remind our members that messages to this list should be (at least
tangentially) on the subject of COMPUTER DESIGN and COMPUTER ARCHITECTURE
using FPGAs. (The mor... Re: Optimal states per bit [7 Articles]
rtstofer - Jul 22 2005
--- In fpga-cpu@fpga..., Veronica Merryfield
Re: Re: Low cost Altera board [4 Articles]
Alex Gibson - Jun 24 2005
John Kent wrote:
> Hi Richard & Alex,
>
> Yes it does look like a nice board.
>
> I was wondering what size the Altera FPGA is in comparison to the Xilinx
> devic... Re: Use for 2 bit opcode ? [4 Articles]
Kolja Sulimma - Apr 2 2005
Rob Finch wrote:
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, bu... bit serial CPUs, anyone? [6 Articles]
Jan Gray - Mar 28 2005
See http://wiki.openchip.org/index.php/Contest:SRL16.
I've been waiting for some tiny bit-serial CPUs to emerge. This is your
chance at fame! (Well, what passes for fam... Ideas For Array Processor [5 Articles]
rtstofer - Mar 17 2005
I am looking into the idea of a maze solving robot. The flood fill
algorithm (see
http://micromouse.cannock.ac.uk/maze/fastfloodsolver.htm ) is simple
en... Re: arithmetic [4 Articles]
Ben Franchuk - Feb 26 2005
Rob Finch wrote:
>
> Has anyone noticed that it's almost as efficient to use sign-
> magnitude arithmetic on an FPGA as it is to use two's complement
> arithm... Re: 1000K Gate Spartan 3 Starter Board Available
rtstofer - Feb 12 2005
--- In , John Kent Re: New to FPGA development [4 Articles]
rtstofer - Jan 26 2005
Not really.
I erased my 'rant' about IO before I posted the message. I
absolutely hate the idea that the JTAG signals are present on EVERY
connector plus ... Re: why FPGA?
- Jan 13 2005
In case anyone is interested, I have completed v1.0 of the assembler
for the custom CPU I am building. I think someone expressed an
interest in the CPU, so I tho... FreeBSD tools ? [2 Articles]
Kathy Quinlan - Jan 11 2005
Hi All,
Once again after M$ Windows XP destroyed its self, I am again thinking
of going back to FreeBSD.
I have my AVR stuff and I can buy a reasonable ... Re: why FPGA? [3 Articles]
- Jan 10 2005
Moved here from armForth group...
--- In , "raimond712002" Re: Spartan reconfiguration
John Kent - Jan 2 2005
Many years ago there was a range of FPGA's brought out by a company called
Algatronics which allowed direct addressing of the switches in the FPGA
array.
Xili... Re: Spartan 3 Starter Kit? [15 Articles]
John Kent - Dec 25 2004
Hi Tony,
The Spartan 3 board is good value for money.
It has 1MByte of Fast SRAM that can be up to 32 bits wide.
It has VGA interface, although rather limitted... Re: Memory Management
Rob Finch - Dec 24 2004
--- In , "James" Re: Xilinx vs Altera / Microblaze vs Nios??? [2 Articles]
James - Dec 15 2004
Mats,
As the Nios II architect and designer, I'm excited that you are
interested in using a soft-core FPGA processor.
I wish I had one of these to play wit...