This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
My friends, the big action these days in loveable programming models for
shared memory synchronization is transactional memory.
http://www.cs.wisc.edu/trans-memory/biblio/index....
Have you ever looked at code guarded by mutexes and semaphores and
wondered, "what if the guarded code were placed in a RAM block that
ensured exclusive access to itself" ?
...
I'm working on a project with the Spartan 3 Starter Board and the
Xilinx WebPack ISE version 8.2
As I look over the timing results, there are lengthy delays in the
paths conta...
I just started playing with Xilinx Spartan 3E (speed grade -4) and I was appalled to find that even with extreme care can I only run the BRAMs at 170 MHz. Anything realistic and th...
Hello
I want to continue exploration of cpu archtectures in my past time and
wondered if anyone knew of a low cost verilog simulator that i could
purchase for home use ?
...
I think I found a relatively painless way to handle oddball bit
widths, like 10 bit bytes, 20 bit instruction words, etc. when using
standard memory parts.
I struggled for a...
I am looking for a 16 bit 2's complement ALU with
add,subtract,multiply and divide as well as the usual shift and
logical operations. This can be in multiple units like the 'yac...
Hi,
If you already know OpenTech then you have to know that the new release
1.6.1 is available now.
OpenTech is the first world wide package of free open source hardware
design...
A barrel processor seems like a natural when the PLD has the ability
to support multi-contexts. All of those "extra" registers are already
just sitting there idle.
It's very...