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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
A bit of history [16 Articles]
veronica_merryfield - Feb 10 2005
Mostly. This is neat
http://news.com.com/Hobbyist+reconstructs+Apollos+computer/2100-
1003_3-5570963.html?tag=nefd.top
and so are some of the links ... 
Request for comments: 16-bit cpu arch
Umair siddiqui - Feb 8 2005
Require comments on given instruction set (cheated
from many areas - including
Hennessy & Patterson comp arch book)for datapath
*simplificaton* and
less cl... Experiences with the Altera UP3-board and NiosII [4 Articles]
Mats Brorsson - Feb 3 2005
Hi,
I was wondering if anyone has experiences using the Altera UP3-board
with NiosII? Any comments are welcome. I'm looking for an
educational board suita... Why no links or files here?
- Jan 29 2005
Is there a reason that the links and files portion of this group is
not enabled? I would expect a list of links could be very useful. I
can do my own searches, b... vmebus master softcore - reg [6 Articles]
kannaiah badam - Jan 24 2005
Hello to all the fpga designers
we are planning to design Motorola Power PC8260 based
200 Mhz, cpu board on VME bus. we would like to use
vmebus master in a fp... Re: Re: why FPGA? -- oops
Jan Gray - Jan 23 2005
Sorry about that, folks. I inadvertently send a personal reply to the whole
list.
While I'm bothering you all, I'd wish to gently steer our focus back towards ... Re: Re: why FPGA?
Jan Gray - Jan 23 2005
Hi Austin. It is very kind of you to contribute your considerable expertise
to the list. Thank you!
Jan.
... New to FPGA development [16 Articles]
sirtiffguy - Jan 23 2005
Hey guys (newby here),
I am looking for a cheep development board with a few cool additions
on it. My sole reason (one of them anyway) is to move from cod... OT: verilog arrays [3 Articles]
Rob Finch - Jan 22 2005
Does anyone know how to pass arrays to a module in Verilog ? I tried
this as a test but it doesn't work:
module arrayTest(s, a, o);
input [2:0] s;
input ...