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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
[morphware] deadline for submissions: May 12 - Reconfigurable Computing
Reiner Hartenstein - May 9 2006
ReCoSoC'06
Reconfigurable Communication-centric SoCs
July 3 - 5, 2006, Montpellier, France
http://www.lirmm.fr/RECOSOC06/
deadline... ![[morphware] deadline for submissions: May 12 - Reconfigurable Computing](http://cdn.embeddedrelated.com/images/icon_more.jpg){kind=icon}
help - creating macros [2 Articles]
harish - Apr 15 2006
Hi guys,
i have a small query. i have a small design and i have to place this
design and compact it to the left most corner of the FPGA. i did this
using the FPGA Editor, by... implementing memory mapped register [6 Articles]
windam_2000 - Apr 15 2006
Hi All,
I'm new to fpga design and was trying to research on logic on how to
implement several memory mapped registers on an FPGA. I'm trying not
to take shortcuts by relying ... OR1200 Test bench [3 Articles]
Balaji Iyer - Mar 9 2006
Hi Everyone,
Is anyone here using (or used in the past) OR 1200 by OpenRISC? If
so, have you written a testbench to test it?
If you have done so, can you please be wi... Re: Query on FPGA testing after configure it.
juendme - Dec 18 2005
The best way to test an FPGA design running on the chip is to use one
of the on-chip analyzers. If you're using Altera's FPGAs, try
SignalTap II
( http://www.altera.com/p... Need help ?? [3 Articles]
MAHADEV - Dec 6 2005
i need help for my seminar topic FPGA for DSP Application ??
if any one have related to this topic plz send it me as soon as
possible.
... Re: Wishbone comments - SimpCon [3 Articles]
Martin Schoeberl - Dec 6 2005
Hi Kolja and all,
>
>> to get a draft of your spec.
...
> The draft of the spec at the moment are few sketches on real
> paper - takes some time to draw all diagr... Wishbone comments [8 Articles]
Martin Schoeberl - Nov 27 2005
After implementing the Wishbone interface for main memory access
from JOP I see several issues with the Wishbone specification that
makes it not the best choice for SoC inte... Good day
a.be...@... - Nov 23 2005
The message cannot be represented in 7-bit ASCII encoding and has been sent as a binary attachment.
[Non-text portions of this message have been removed]
... Conectivity - Register, OPB,dip switch [2 Articles]
ramt...@... - Oct 29 2005
Hi
I am looking for some help with the microblaze processor. I need to connect the registers on the microblaze processor to recieve input from the switches on the the boar...