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Discussion Groups | LPC900 | LPC924 as I2C slave issues
Find help, specifications and source code for the LPC900. The LPC900 challenges Microchip and AVR based on the worlds most popular 8-bit architecture the 80C51. With a 2-clock core the LPC900 series is a high performance, very flexible and low cost 8-bit microcontroller family. Designers using or interested in these devices are encouraged to share their know-how and ask questions.
LPC924 as I2C slave issues - syzlak_icd - Nov 25 13:37:44 2006
I am using the 924 as an I2C slave device and am running into a very
strange problem!! The 924 will give an ACK to it's own address but
immediately after the ACK it pulls the SCL line low as if doing
clock stretching, but it NEVER releases it! I have read the data
sheet, read app notes and searched every where I can think of with
no luck. I have coded this in both C and assembly with (of course)
identical result. Well I will list here the I2C interrupt routine
for your viewing pleasure... if anybody can spot the problem I would
be very grateful.
StackTop DATA 50h
; Reset
CSEG AT 00h
LJMP Reset
; I2C interrupt
; org 36h
CSEG AT 0036h
PUSH PSW ; Save status.
PUSH ACC ; Save accumulator.
ACALL I2C_Handle
POP ACC
POP PSW
RETI
;--------------------------------------------------------------------
; Main Program
;--------------------------------------------------------------------
Reset:
MOV SP,#StackTop ; Set stack location.
ORL P1M1,#0Ch ; Configure SDA &
SCL pins
ORL P1M2,#0Ch
ORL P3M1,#0x03;
ORL P3M2,#0x03;
MOV A,#28h ; Configure I2C
Address
CLR C
RLC A
MOV I2ADR,A
MOV I2SCLH,#05H ; Configure SCL Generator
MOV I2SCLL,#04H ; (using internal generator)
MOV I2CON,#45h
ANL IP1,#0FEh ; Set interrupt priority to 0
ANL IP1H,#0FEh
SETB EI2C
DoNothing:
JMP DoNothing
I2C_Handle:
CLR STA
CLR STO
CLR AA
CLR SI
MOV I2DAT,A
RET
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strange problem!! The 924 will give an ACK to it's own address but
immediately after the ACK it pulls the SCL line low as if doing
clock stretching, but it NEVER releases it! I have read the data
sheet, read app notes and searched every where I can think of with
no luck. I have coded this in both C and assembly with (of course)
identical result. Well I will list here the I2C interrupt routine
for your viewing pleasure... if anybody can spot the problem I would
be very grateful.
StackTop DATA 50h
; Reset
CSEG AT 00h
LJMP Reset
; I2C interrupt
; org 36h
CSEG AT 0036h
PUSH PSW ; Save status.
PUSH ACC ; Save accumulator.
ACALL I2C_Handle
POP ACC
POP PSW
RETI
;--------------------------------------------------------------------
; Main Program
;--------------------------------------------------------------------
Reset:
MOV SP,#StackTop ; Set stack location.
ORL P1M1,#0Ch ; Configure SDA &
SCL pins
ORL P1M2,#0Ch
ORL P3M1,#0x03;
ORL P3M2,#0x03;
MOV A,#28h ; Configure I2C
Address
CLR C
RLC A
MOV I2ADR,A
MOV I2SCLH,#05H ; Configure SCL Generator
MOV I2SCLL,#04H ; (using internal generator)
MOV I2CON,#45h
ANL IP1,#0FEh ; Set interrupt priority to 0
ANL IP1H,#0FEh
SETB EI2C
DoNothing:
JMP DoNothing
I2C_Handle:
CLR STA
CLR STO
CLR AA
CLR SI
MOV I2DAT,A
RET
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Re: LPC924 as I2C slave issues - phb_miller - Nov 26 17:30:19 2006
Couple of things stand out:
> MOV I2SCLH,#05H ; Configure SCL Generator
> MOV I2SCLL,#04H ; (using internal generator)
>
> MOV I2CON,#45h
OK - from the values written you are intending to use the internal
I2C bus clock generator BUT you have enabled the T1 overflow as the
clock source so the values in I2SCL will be ignored (and not enabled
T1). For this configuration CRSEL = 0, and I suspect that clearing
this bit in the control word would be a good start.
The data sheet states that CRSEL is not used in slave mode. I don't
agree as the acknowledge pulse would be generated and therefore timed
by the slave.
> I2C_Handle:
> CLR STA
> CLR STO
> CLR AA
> CLR SI
> MOV I2DAT,A
> RET
Looks all together too simplistic - have a good read of the status
values and responses your code needs to do.
Remember - as a SLAVE you HAVE to generate the ACK for the address,
and from then on you have to generate (or process) the ACK depending
on the data direction.
PM
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> MOV I2SCLH,#05H ; Configure SCL Generator
> MOV I2SCLL,#04H ; (using internal generator)
>
> MOV I2CON,#45h
OK - from the values written you are intending to use the internal
I2C bus clock generator BUT you have enabled the T1 overflow as the
clock source so the values in I2SCL will be ignored (and not enabled
T1). For this configuration CRSEL = 0, and I suspect that clearing
this bit in the control word would be a good start.
The data sheet states that CRSEL is not used in slave mode. I don't
agree as the acknowledge pulse would be generated and therefore timed
by the slave.
> I2C_Handle:
> CLR STA
> CLR STO
> CLR AA
> CLR SI
> MOV I2DAT,A
> RET
Looks all together too simplistic - have a good read of the status
values and responses your code needs to do.
Remember - as a SLAVE you HAVE to generate the ACK for the address,
and from then on you have to generate (or process) the ACK depending
on the data direction.
PM
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )