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Discussion Groups | LPC900 | SPI read action
Find help, specifications and source code for the LPC900. The LPC900 challenges Microchip and AVR based on the worlds most popular 8-bit architecture the 80C51. With a 2-clock core the LPC900 series is a high performance, very flexible and low cost 8-bit microcontroller family. Designers using or interested in these devices are encouraged to share their know-how and ask questions.
SPI read action - yen0yuki - Jun 6 5:32:00 2006
Dear ALL,
I try to use SPI function with LPC932.
Transfer was success.
Data is watched on MOSI pin.
However, receive was fail.
Data is not watched on MISO pin.
dummy data is send.
source is follow.
------
// dummy data
SPDAT=dat;
while(! (SPSTAT & 0x80))
;
SPSTAT |= 0x80;
// Wait until the SPIF Flag is on
dat=SPDAT; /* debug */
------
please advice me.
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
I try to use SPI function with LPC932.
Transfer was success.
Data is watched on MOSI pin.
However, receive was fail.
Data is not watched on MISO pin.
dummy data is send.
source is follow.
---
// dummy data
SPDAT=dat;
while(! (SPSTAT & 0x80))
;
SPSTAT |= 0x80;
// Wait until the SPIF Flag is on
dat=SPDAT; /* debug */
------
please advice me.
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
Re: SPI read action - Pramod - Jun 7 2:33:47 2006
Hi,
I have interfaced a 89LV51RD2 to 89LPC932 using SPI.
For this I had to spend some time tweaking register values till it
worked.
However the data received is never exactly what you send, but a
workaround does the trick.
See if the code snippet is of any help.
// LPC side
// ----------------------- Configure Slave ---------------------------
void spi_init( void)
{
// set MOSI, MISO, /SS and SPICLK as quasi-bidirectional
P2M1 &= 0xC3;
P2M2 &= 0xC3;
// configure SPI
// 12.2 Additional considerations for a slave
// When CPHA equals zero, SSIG must be logic 0 and the SS pin must be
negated and
// reasserted between each successive serial byte. If the SPDAT
register is written while SS
// is active (low), a write collision error results. The operation is
undefined if CPHA is logic 0
// and SSIG is logic 1.
SPCTL = 0x49; // 0100 1001 works for WR_RD with LV51 set to (
0x51..0x53)
// When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0, the
SS pin may remain
// active low between successive transfers (can be tied low at all
times). This format is
// sometimes preferred in systems having a single fixed master and a
single slave driving
// the MISO data line.
//SPCTL = 0x4D;
// set SPI interrupt priority to 3
IP1 &= ~0x08;
IP1H &= ~0x08;
IP1 |= 0x08;
IP1H |= 0x08;
/*
// set SPI interrupt priority to 0
IP1 &= ~0x08;
IP1H &= ~0x08;
*/
// enable SPI interrupt
ESPI = 1;
} // spi_init
//------------------------------------------------------------------
static void spi_isr( void) interrupt 9 using 3
{
S8 xdata temp;
// clear SPIF bit by writing 1 to it
SPSTAT |= 0x80;
// wait SPIDIS = 240 nS
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
temp = _cror_( SPDAT, 1); // this is the workaround
while( B_SS == 0){;}
// wait SPILAG = 240 nS
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
SPDAT = ~temp; // to verify on LV51 side
} // spi_isr
--- In l...@yahoogroups.com, "yen0yuki" wrote:
>
> Dear ALL,
>
> I try to use SPI function with LPC932.
>
> Transfer was success.
> Data is watched on MOSI pin.
>
> However, receive was fail.
> Data is not watched on MISO pin.
> dummy data is send.
> source is follow.
>
> ------
>
> // dummy data
> SPDAT=dat;
> while(! (SPSTAT & 0x80))
> ;
>
> SPSTAT |= 0x80;
>
> // Wait until the SPIF Flag is on
> dat=SPDAT; /* debug */
>
> ------
>
> please advice me.
>
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
I have interfaced a 89LV51RD2 to 89LPC932 using SPI.
For this I had to spend some time tweaking register values till it
worked.
However the data received is never exactly what you send, but a
workaround does the trick.
See if the code snippet is of any help.
// LPC side
// ----------------------- Configure Slave ---------------------------
void spi_init( void)
{
// set MOSI, MISO, /SS and SPICLK as quasi-bidirectional
P2M1 &= 0xC3;
P2M2 &= 0xC3;
// configure SPI
// 12.2 Additional considerations for a slave
// When CPHA equals zero, SSIG must be logic 0 and the SS pin must be
negated and
// reasserted between each successive serial byte. If the SPDAT
register is written while SS
// is active (low), a write collision error results. The operation is
undefined if CPHA is logic 0
// and SSIG is logic 1.
SPCTL = 0x49; // 0100 1001 works for WR_RD with LV51 set to (
0x51..0x53)
// When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0, the
SS pin may remain
// active low between successive transfers (can be tied low at all
times). This format is
// sometimes preferred in systems having a single fixed master and a
single slave driving
// the MISO data line.
//SPCTL = 0x4D;
// set SPI interrupt priority to 3
IP1 &= ~0x08;
IP1H &= ~0x08;
IP1 |= 0x08;
IP1H |= 0x08;
/*
// set SPI interrupt priority to 0
IP1 &= ~0x08;
IP1H &= ~0x08;
*/
// enable SPI interrupt
ESPI = 1;
} // spi_init
//------------------------------------------------------------------
static void spi_isr( void) interrupt 9 using 3
{
S8 xdata temp;
// clear SPIF bit by writing 1 to it
SPSTAT |= 0x80;
// wait SPIDIS = 240 nS
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
temp = _cror_( SPDAT, 1); // this is the workaround
while( B_SS == 0){;}
// wait SPILAG = 240 nS
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
SPDAT = ~temp; // to verify on LV51 side
} // spi_isr
--- In l...@yahoogroups.com, "yen0yuki"
>
> Dear ALL,
>
> I try to use SPI function with LPC932.
>
> Transfer was success.
> Data is watched on MOSI pin.
>
> However, receive was fail.
> Data is not watched on MISO pin.
> dummy data is send.
> source is follow.
>
> ---
>
> // dummy data
> SPDAT=dat;
> while(! (SPSTAT & 0x80))
> ;
>
> SPSTAT |= 0x80;
>
> // Wait until the SPIF Flag is on
> dat=SPDAT; /* debug */
>
> ------
>
> please advice me.
>
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
Re: SPI read action - yen0yuki - Jun 8 0:12:44 2006
Dear Pramod,
Thank you for your advice.
This problem is solved.
Peripferal has problem.
It was able to communicate bySPI.
regards,
--- In l...@yahoogroups.com, "Pramod" wrote:
>
> Hi,
> I have interfaced a 89LV51RD2 to 89LPC932 using SPI.
> For this I had to spend some time tweaking register values till it
> worked.
> However the data received is never exactly what you send, but a
> workaround does the trick.
> See if the code snippet is of any help.
> // LPC side
>
> // ----------------------- Configure Slave ------------------------
---
> void spi_init( void)
> {
>
> // set MOSI, MISO, /SS and SPICLK as quasi-bidirectional
> P2M1 &= 0xC3;
> P2M2 &= 0xC3;
>
>
> // configure SPI
>
> // 12.2 Additional considerations for a slave
> // When CPHA equals zero, SSIG must be logic 0 and the SS pin must
be
> negated and
> // reasserted between each successive serial byte. If the SPDAT
> register is written while SS
> // is active (low), a write collision error results. The operation
is
> undefined if CPHA is logic 0
> // and SSIG is logic 1.
>
> SPCTL = 0x49; // 0100 1001 works for WR_RD with LV51 set to (
> 0x51..0x53)
> // When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0,
the
> SS pin may remain
> // active low between successive transfers (can be tied low at all
> times). This format is
> // sometimes preferred in systems having a single fixed master and
a
> single slave driving
> // the MISO data line.
>
> //SPCTL = 0x4D;
> // set SPI interrupt priority to 3
> IP1 &= ~0x08;
> IP1H &= ~0x08;
> IP1 |= 0x08;
> IP1H |= 0x08;
>
> /*
> // set SPI interrupt priority to 0
> IP1 &= ~0x08;
> IP1H &= ~0x08;
> */
>
> // enable SPI interrupt
> ESPI = 1;
> } // spi_init
> //-----------------------------------------------------------------
-
>
> static void spi_isr( void) interrupt 9 using 3
> {
> S8 xdata temp;
>
> // clear SPIF bit by writing 1 to it
> SPSTAT |= 0x80;
> // wait SPIDIS = 240 nS
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
> temp = _cror_( SPDAT, 1); // this is the workaround
>
> while( B_SS == 0){;}
> // wait SPILAG = 240 nS
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
>
> SPDAT = ~temp; // to verify on LV51 side
> } // spi_isr
> --- In l...@yahoogroups.com, "yen0yuki" wrote:
> >
> > Dear ALL,
> >
> > I try to use SPI function with LPC932.
> >
> > Transfer was success.
> > Data is watched on MOSI pin.
> >
> > However, receive was fail.
> > Data is not watched on MISO pin.
> > dummy data is send.
> > source is follow.
> >
> > ------
> >
> > // dummy data
> > SPDAT=dat;
> > while(! (SPSTAT & 0x80))
> > ;
> >
> > SPSTAT |= 0x80;
> >
> > // Wait until the SPIF Flag is on
> > dat=SPDAT; /* debug */
> >
> > ------
> >
> > please advice me.
>
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )
Thank you for your advice.
This problem is solved.
Peripferal has problem.
It was able to communicate bySPI.
regards,
--- In l...@yahoogroups.com, "Pramod"
>
> Hi,
> I have interfaced a 89LV51RD2 to 89LPC932 using SPI.
> For this I had to spend some time tweaking register values till it
> worked.
> However the data received is never exactly what you send, but a
> workaround does the trick.
> See if the code snippet is of any help.
> // LPC side
>
> // ----------------------- Configure Slave ------------------------
---
> void spi_init( void)
> {
>
> // set MOSI, MISO, /SS and SPICLK as quasi-bidirectional
> P2M1 &= 0xC3;
> P2M2 &= 0xC3;
>
>
> // configure SPI
>
> // 12.2 Additional considerations for a slave
> // When CPHA equals zero, SSIG must be logic 0 and the SS pin must
be
> negated and
> // reasserted between each successive serial byte. If the SPDAT
> register is written while SS
> // is active (low), a write collision error results. The operation
is
> undefined if CPHA is logic 0
> // and SSIG is logic 1.
>
> SPCTL = 0x49; // 0100 1001 works for WR_RD with LV51 set to (
> 0x51..0x53)
> // When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0,
the
> SS pin may remain
> // active low between successive transfers (can be tied low at all
> times). This format is
> // sometimes preferred in systems having a single fixed master and
a
> single slave driving
> // the MISO data line.
>
> //SPCTL = 0x4D;
> // set SPI interrupt priority to 3
> IP1 &= ~0x08;
> IP1H &= ~0x08;
> IP1 |= 0x08;
> IP1H |= 0x08;
>
> /*
> // set SPI interrupt priority to 0
> IP1 &= ~0x08;
> IP1H &= ~0x08;
> */
>
> // enable SPI interrupt
> ESPI = 1;
> } // spi_init
> //-----------------------------------------------------------------
-
>
> static void spi_isr( void) interrupt 9 using 3
> {
> S8 xdata temp;
>
> // clear SPIF bit by writing 1 to it
> SPSTAT |= 0x80;
> // wait SPIDIS = 240 nS
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
> temp = _cror_( SPDAT, 1); // this is the workaround
>
> while( B_SS == 0){;}
> // wait SPILAG = 240 nS
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
> _nop_ ();
>
> SPDAT = ~temp; // to verify on LV51 side
> } // spi_isr
> --- In l...@yahoogroups.com, "yen0yuki"
> >
> > Dear ALL,
> >
> > I try to use SPI function with LPC932.
> >
> > Transfer was success.
> > Data is watched on MOSI pin.
> >
> > However, receive was fail.
> > Data is not watched on MISO pin.
> > dummy data is send.
> > source is follow.
> >
> > ---
> >
> > // dummy data
> > SPDAT=dat;
> > while(! (SPSTAT & 0x80))
> > ;
> >
> > SPSTAT |= 0x80;
> >
> > // Wait until the SPIF Flag is on
> > dat=SPDAT; /* debug */
> >
> > ------
> >
> > please advice me.
>
(You need to be a member of LPC900_users -- send a blank email to LPC900_users-subscribe@yahoogroups.com )