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Discussion Groups | AT91SAM ARM | AT91SAM9260 and ADS1278 - AQ in random position in memory

For users of the Atmel AT91SAM7 and AT91SAM9 ARM CPU chips. Atmel has taken a new direction by combining on chip flash and ram with the ARM CPU on a single die. This provides low cost devices for small systems using the ARM CPU. This group is to exchange information to help users get started and learn how to use the devices.

AT91SAM9260 and ADS1278 - AQ in random position in memory - =?ISO-8859-1?Q?Alex Ruiz?= - May 12 17:09:57 2008

Hallo,

I'm using AT91SAM9160's SSC interface in Frame-Sync mode in order to interface an ADS1278 (24-bit ) converter operating in

TDM fixed-mode ( All eight AD channels will be sent over DOUT1 pin one after the other ) doing max 128kSPS.

The ADS1278 is continuously receiving SCLK, CLK and FSYNC signals.
I'm using RK0 to provide SCLK and CLK, RF0 to provide FSYNC and RD0 to collect ADC data via DOUT1.

The problem I'm experiencing is related to the ADC channel information sequence that is being placed in memory buffer by PDC

(DMA). The information seens to be out of sync, if I put the maximum positive value at the first channel CH1, leave all the

other seven channels floating, and do several convertions, I can see that conversion value from CH1 will be put at random

array's position. No data is lost though, all eight channels are converted correctly. This behavior can be noticed by using

any CH1-CH8 or even in pars CH1 and CH2, CH1 and CH8.

ex.:
U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */

1st) eight channel aquisition run, CH1 will be placed at:

adc_raw[0]=
0x007FFFFF

2nd) run:
adc_raw[6]=
0x007FFFFF

3rd) run:
adc_raw[4]=
0x007FFFFF

4th) run:
adc_raw[2]=
0x007FFFFF

Checking with a Scope I can see that the ADC channel sequence is correct.
The information is comming out of the ADS in a correct sequence.
CH1 CH2 CH3 CH4 CH5 CH6 CH7 Ch8 ( MSB First )...

Have anyone experienced similar problem?

Bellow is a piece showing my configuration parameters:

/*--------------------------------------------------------------------
--------------------------------------------------------------------*/
#include /* AT91SAM9260 definitions */
#include /* Library function definitions */
#include
#include

/*--------------------------------------------------------------------
Configuration parameters for ADS1278 interface via SSC frame_sync
--------------------------------------------------------------------*/
#define MCK 96109714 /* Main clock frequency in Hz */

#define SAMPLE_FREQ 25000
#define HIGH_SPEED 256 /* fCLK/fDATA = 256*/
#define SLOT_BY_FRAME 8 /* Number of ADC CHannels */
#define BITS_BY_SLOT 24

/*--------------------------------------------------------------------
Config dos resistros de hardware
--------------------------------------------------------------------*/
#define PERIOD ((U32)(((SLOT_BY_FRAME*BITS_BY_SLOT)/2)-1) << 24)
#define CKS_DIVIDED_CLOCK ((U32)0<<0)
#define CKO_CONTINUOUS ((U32)1<<2)
#define CKO_ONLY_ON_DATA_TRANSFER ((U32)2<<2)
#define CKI_SAMPLE_FALLING_EDGE ((U32)0<<5)
#define CKG_NO_CLOCK_GATE ((U32)0<<6)
#define STOP_RX ((U32)0<<12)
#define RFMR_DATLEN ((U32)(BITS_BY_SLOT-1)<<0)
#define RFMR_LOOP ((U32)0<<5)
#define RFMR_MSBF ((U32)1<<7)
#define RFMR_DATNB ((U32)(SLOT_BY_FRAME-1)<<8)
#define RFMR_FSLEN ((U32)0<<16)
#define RFMR_FSOS ((U32)2<<20)
#define RFMR_FSEDGE ((U32)0<<24)
/*--------------------------------------------------------------------
Buffer de recepcao de dados do ADS1278
--------------------------------------------------------------------*/
#define ADS_UMA_AMOSTRA 8
#define ADS_N_AMOSTRAS 1
#define BUF_SIZE ( ADS_UMA_AMOSTRA*ADS_N_AMOSTRAS )

U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */
U32 adc_raw2[BUF_SIZE];
/*--------------------------------------------------------------------
--------------------------------------------------------------------*/
void SSC_Configura ( void )
{
AT91F_SSC0_CfgPIO ();
AT91F_PIO_CfgPullup (AT91C_BASE_PIOB, AT91C_PB20_RK0);
AT91F_SSC0_CfgPMC ();
AT91C_BASE_SSC0->SSC_CR = AT91C_SSC_SWRST;
AT91F_PDC_Close((AT91PS_PDC) &(AT91C_BASE_SSC0->SSC_RPR));

AT91F_SSC_SetBaudrate ( AT91C_BASE_SSC0, MCK, SAMPLE_FREQ * HIGH_SPEED );

/* Confige for ADS1278 frame-sync */
AT91C_BASE_SSC0->SSC_RCMR = ( (( CKS_DIVIDED_CLOCK)& AT91C_SSC_CKS) |
(( CKO_CONTINUOUS)& AT91C_SSC_CKO) |
(( CKI_SAMPLE_FALLING_EDGE)& AT91C_SSC_CKI) |
(( CKG_NO_CLOCK_GATE)& ((U32) 0x3 << 6)) |
(( AT91C_SSC_START_RISE_RF)& AT91C_SSC_START) |
(( STOP_RX)& AT91C_SSC_STOP) |
(( PERIOD)& AT91C_SSC_PERIOD)
);
AT91C_BASE_SSC0->SSC_RFMR = ( ((RFMR_DATLEN)& AT91C_SSC_DATLEN) |
((RFMR_LOOP)& AT91C_SSC_LOOP) |
((RFMR_MSBF)& AT91C_SSC_MSBF) |
((RFMR_DATNB)& AT91C_SSC_DATNB) |
((RFMR_FSLEN)& AT91C_SSC_FSLEN) |
((RFMR_FSOS)& AT91C_SSC_FSOS)
);
/*--------------------------------------------------------------------
Enable DMA transfer
--------------------------------------------------------------------*/
AT91F_PDC_SetRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw1, BUF_SIZE);
AT91F_PDC_SetNextRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw2, BUF_SIZE);
AT91F_PDC_EnableRx (AT91C_BASE_PDC_SSC0); /* Enable the PDC feature */
AT91F_SSC_EnableRx ( AT91C_BASE_SSC0 );
}
/*--------------------------------------------------------------------
--------------------------------------------------------------------*/
int main ( void )
{

SSC_Configura();

while(1)
{
AT91F_SSC_ReceiveFrame (AT91C_BASE_SSC0, (S8*)adc_raw1, BUF_SIZE, (S8*)adc_raw2, BUF_SIZE);
}
}
/*--------------------------------------------------------------------
--------------------------------------------------------------------*/

Any help would be much appreciated.
Alex

------------------------------------



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Re: AT91SAM9260 and ADS1278 - AQ in random position in memory - Caglar Akyuz - May 12 18:38:09 2008

Alex Ruiz wrote:

> Hallo,
>
Hello,

> I'm using AT91SAM9160's SSC interface in Frame-Sync mode in order to
> interface an ADS1278 (24-bit ) converter operating in
>
I would prefer SPI for this connection though I don't remember signaling
of frame-sync. Anyway, I tried to comment on the relevant lines in your code,
please follow.

> TDM fixed-mode ( All eight AD channels will be sent over DOUT1 pin one
> after the other ) doing max 128kSPS.
>
> The ADS1278 is continuously receiving SCLK, CLK and FSYNC signals.
> I'm using RK0 to provide SCLK and CLK, RF0 to provide FSYNC and RD0 to
> collect ADC data via DOUT1.
>
> The problem I'm experiencing is related to the ADC channel information
> sequence that is being placed in memory buffer by PDC
>
> (DMA). The information seens to be out of sync, if I put the maximum
> positive value at the first channel CH1, leave all the
>
> other seven channels floating, and do several convertions, I can see
> that conversion value from CH1 will be put at random
>
> array's position. No data is lost though, all eight channels are
> converted correctly. This behavior can be noticed by using
>
> any CH1-CH8 or even in pars CH1 and CH2, CH1 and CH8.
>
> ex.:
> U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */
>

> 1st) eight channel aquisition run, CH1 will be placed at:
>
> adc_raw[0]=
> 0x007FFFFF
>
I think this is adc_raw1...

> 2nd) run:
> adc_raw[6]=
> 0x007FFFFF
>
adc_raw1 again...

> 3rd) run:
> adc_raw[4]=
> 0x007FFFFF
>
and this is adc_raw2...

> 4th) run:
> adc_raw[2]=
> 0x007FFFFF
>
and this is adc_raw1 also...

> Checking with a Scope I can see that the ADC channel sequence is correct.
> The information is comming out of the ADS in a correct sequence.
> CH1 CH2 CH3 CH4 CH5 CH6 CH7 Ch8 ( MSB First )...
>
> Have anyone experienced similar problem?
>
> Bellow is a piece showing my configuration parameters:
>
> /*----------------------------------------------------------
> ----------------------------------------------------------*/
> #include /* AT91SAM9260 definitions */
> #include /* Library function definitions */
> #include
> #include /*----------------------------------------------------------
> Configuration parameters for ADS1278 interface via SSC frame_sync
> ----------------------------------------------------------*/
> #define MCK 96109714 /* Main clock frequency in Hz */
>
> #define SAMPLE_FREQ 25000
> #define HIGH_SPEED 256 /* fCLK/fDATA = 256*/
> #define SLOT_BY_FRAME 8 /* Number of ADC CHannels */
> #define BITS_BY_SLOT 24
>
> /*----------------------------------------------------------
> Config dos resistros de hardware
> ----------------------------------------------------------*/
> #define PERIOD ((U32)(((SLOT_BY_FRAME*BITS_BY_SLOT)/2)-1) << 24)
> #define CKS_DIVIDED_CLOCK ((U32)0<<0)
> #define CKO_CONTINUOUS ((U32)1<<2)
> #define CKO_ONLY_ON_DATA_TRANSFER ((U32)2<<2)
> #define CKI_SAMPLE_FALLING_EDGE ((U32)0<<5)
> #define CKG_NO_CLOCK_GATE ((U32)0<<6)
> #define STOP_RX ((U32)0<<12)
> #define RFMR_DATLEN ((U32)(BITS_BY_SLOT-1)<<0)

> #define RFMR_LOOP ((U32)0<<5)
> #define RFMR_MSBF ((U32)1<<7)
> #define RFMR_DATNB ((U32)(SLOT_BY_FRAME-1)<<8)
> #define RFMR_FSLEN ((U32)0<<16)
> #define RFMR_FSOS ((U32)2<<20)
> #define RFMR_FSEDGE ((U32)0<<24)
> /*----------------------------------------------------------
> Buffer de recepcao de dados do ADS1278
> ----------------------------------------------------------*/
> #define ADS_UMA_AMOSTRA 8
> #define ADS_N_AMOSTRAS 1
> #define BUF_SIZE ( ADS_UMA_AMOSTRA*ADS_N_AMOSTRAS )
hımm, you're defining BUF_SIZE as 8...

>
> U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */
> U32 adc_raw2[BUF_SIZE];
> /*----------------------------------------------------------
> ----------------------------------------------------------*/
> void SSC_Configura ( void )
> {
> AT91F_SSC0_CfgPIO ();
> AT91F_PIO_CfgPullup (AT91C_BASE_PIOB, AT91C_PB20_RK0);
> AT91F_SSC0_CfgPMC ();
> AT91C_BASE_SSC0->SSC_CR = AT91C_SSC_SWRST;
> AT91F_PDC_Close((AT91PS_PDC) &(AT91C_BASE_SSC0->SSC_RPR));
>
> AT91F_SSC_SetBaudrate ( AT91C_BASE_SSC0, MCK, SAMPLE_FREQ * HIGH_SPEED );
>
> /* Confige for ADS1278 frame-sync */
> AT91C_BASE_SSC0->SSC_RCMR = ( (( CKS_DIVIDED_CLOCK)& AT91C_SSC_CKS) |
> (( CKO_CONTINUOUS)& AT91C_SSC_CKO) |
> (( CKI_SAMPLE_FALLING_EDGE)& AT91C_SSC_CKI) |
> (( CKG_NO_CLOCK_GATE)& ((U32) 0x3 << 6)) |
> (( AT91C_SSC_START_RISE_RF)& AT91C_SSC_START) |
> (( STOP_RX)& AT91C_SSC_STOP) |
> (( PERIOD)& AT91C_SSC_PERIOD)
> );
> AT91C_BASE_SSC0->SSC_RFMR = ( ((RFMR_DATLEN)& AT91C_SSC_DATLEN) |
> ((RFMR_LOOP)& AT91C_SSC_LOOP) |
> ((RFMR_MSBF)& AT91C_SSC_MSBF) |
> ((RFMR_DATNB)& AT91C_SSC_DATNB) |
> ((RFMR_FSLEN)& AT91C_SSC_FSLEN) |
> ((RFMR_FSOS)& AT91C_SSC_FSOS)
> );
> /*----------------------------------------------------------
> Enable DMA transfer
> ----------------------------------------------------------*/
> AT91F_PDC_SetRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw1, BUF_SIZE);
> AT91F_PDC_SetNextRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw2, BUF_SIZE);
> AT91F_PDC_EnableRx (AT91C_BASE_PDC_SSC0); /* Enable the PDC feature */
> AT91F_SSC_EnableRx ( AT91C_BASE_SSC0 );
> }
> /*----------------------------------------------------------
> ----------------------------------------------------------*/
> int main ( void )
> {
>
> SSC_Configura();
>
> while(1)
> {
> AT91F_SSC_ReceiveFrame (AT91C_BASE_SSC0, (S8*)adc_raw1, BUF_SIZE,
> (S8*)adc_raw2, BUF_SIZE);
Now you're receiving 32 bytes to 1st buffer, then switching to the
next buffer, receiving 32 bytes to it, etc. So first 24 bytes in buffer 1
second 24 bytes block is spread into buffer 1 and 2(first 8 bytes in buffer 1
and last 16 bytes in buffer two), etc... So it's normal that every sample of
your any channel shifts 8 bytes left(thinking your adc_raw buffers as circular
buffers)

I may be wrong but this is what I see when I analyze your code. I hope this helps.
BTW, your ADC samples are not byte aligned, they are aligned on a 3 bytes boundary, so
receiving samples into an integer buffer will not work for all channels so easily.
Be careful for alignment errors. Turning on an extra status byte for each channel
on ADS1278 may help, though I don't know if it is possible. It was possible for ADS1258.

Regards,
Caglar

------------------------------------



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Re: AT91SAM9260 and ADS1278 - AQ in random position in memory - =?ISO-8859-1?Q?Alex Ruiz?= - May 14 7:53:39 2008








Caglar,



Your feedback didn't help me much but it made me think more about what was going on.



It's not possible to use SPI in this case because of the number of KSPS. Frame-Sync is much easier and much faster to use than SPI. 128KSPS is only possible to achieve using Frame-Sync format.



The alignment is not an issue here because any SSC PDC transfer longer than 16 bits will transferred as being four bytes so a word alignment is respected all the time. At the beginning I was going to use SPI and at that time I had the same wrong impression about the 24bit information that would come from the ADC using SSC.





I found what the problem is, it's related to the JTAG debugging. It's NOT possible to stop any peripheral when the CORE is Halted. The PDC acts as a master and the CORE also acts as a master. When I halt the core via JTAG using a breakpoint for instance, the PDC will continue transferring data working as a master, so once I stop at a breakpoint the PDC will be out of sync.



The aquisition data is being put into the correct array position, but once I stop the core it will mess the sync and this problem will show up anytime I halt the core and try to look at the array context using a watch window.



I hope this helps someone out there to save some ridiculous long debugging hours.



Thanks for the help.



Regards,



Alex Ruiz






Tue, 13 May 2008 01:37:57 +0300, Caglar Akyuz escreveu:









Alex Ruiz wrote:



>

>

> Hallo,

>



Hello,



> I'm using AT91SAM9160's SSC interface in Frame-Sync mode in order to

> interface an ADS1278 (24-bit ) converter operating in

>



I would prefer SPI for this connection though I don't remember signaling

of frame-sync. Anyway, I tried to comment on the relevant lines in your code,

please follow.



> TDM fixed-mode ( All eight AD channels will be sent over DOUT1 pin one

> after the other ) doing max 128kSPS.

>

> The ADS1278 is continuously receiving SCLK, CLK and FSYNC signals.

> I'm using RK0 to provide SCLK and CLK, RF0 to provide FSYNC and RD0 to

> collect ADC data via DOUT1.

>

> The problem I'm experiencing is related to the ADC channel information

> sequence that is being placed in memory buffer by PDC

>

> (DMA). The information seens to be out of sync, if I put the maximum

> positive value at the first channel CH1, leave all the

>

> other seven channels floating, and do several convertions, I can see

> that conversion value from CH1 will be put at random

>

> array's position. No data is lost though, all eight channels are

> converted correctly. This behavior can be noticed by using

>

> any CH1-CH8 or even in pars CH1 and CH2, CH1 and CH8.

>

> ex.:

> U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */

>



> 1st) eight channel aquisition run, CH1 will be placed at:

>

> adc_raw[0]=

> 0x007FFFFF

>



I think this is adc_raw1...



> 2nd) run:

> adc_raw[6]=

> 0x007FFFFF

>



adc_raw1 again...



> 3rd) run:

> adc_raw[4]=

> 0x007FFFFF

>



and this is adc_raw2...



> 4th) run:

> adc_raw[2]=

> 0x007FFFFF

>



and this is adc_raw1 also...



> Checking with a Scope I can see that the ADC channel sequence is correct.

> The information is comming out of the ADS in a correct sequence.

> CH1 CH2 CH3 CH4 CH5 CH6 CH7 Ch8 ( MSB First )...

>

> Have anyone experienced similar problem?

>

> Bellow is a piece showing my configuration parameters:

>

> /*----------------------------------------------------------

> ----------------------------------------------------------*/

> #include H> /* AT91SAM9260 definitions */

> #include
h> /* Library function definitions */

> #include

> #include

>

> /*----------------------------------------------------------

> Configuration parameters for ADS1278 interface via SSC frame_sync

> ----------------------------------------------------------*/

> #define MCK 96109714 /* Main clock frequency in Hz */

>

> #define SAMPLE_FREQ 25000

> #define HIGH_SPEED 256 /* fCLK/fDATA = 256*/

> #define SLOT_BY_FRAME 8 /* Number of ADC CHannels */

> #define BITS_BY_SLOT 24

>

> /*----------------------------------------------------------

> Config dos resistros de hardware

> ----------------------------------------------------------*/

> #define PERIOD ((U32)(((SLOT_BY_FRAME*BITS_BY_SLOT)/2)-1) << 24)

> #define CKS_DIVIDED_CLOCK ((U32)0<<0)

> #define CKO_CONTINUOUS ((U32)1<<2)

> #define CKO_ONLY_ON_DATA_TRANSFER ((U32)2<<2)

> #define CKI_SAMPLE_FALLING_EDGE ((U32)0<<5)

> #define CKG_NO_CLOCK_GATE ((U32)0<<6)

> #define STOP_RX ((U32)0<<12)

> #define RFMR_DATLEN ((U32)(BITS_BY_SLOT-1)<<0)



> #define RFMR_LOOP ((U32)0<<5)

> #define RFMR_MSBF ((U32)1<<7)

> #define RFMR_DATNB ((U32)(SLOT_BY_FRAME-1)<<8)

> #define RFMR_FSLEN ((U32)0<<16)

> #define RFMR_FSOS ((U32)2<<20)

> #define RFMR_FSEDGE ((U32)0<<24)

> /*----------------------------------------------------------

> Buffer de recepcao de dados do ADS1278

> ----------------------------------------------------------*/

> #define ADS_UMA_AMOSTRA 8

> #define ADS_N_AMOSTRAS 1

> #define BUF_SIZE ( ADS_UMA_AMOSTRA*ADS_N_AMOSTRAS )



hımm, you're defining BUF_SIZE as 8...



>

> U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */

> U32 adc_raw2[BUF_SIZE];

> /*----------------------------------------------------------

> ----------------------------------------------------------*/

> void SSC_Configura ( void )

> {

> AT91F_SSC0_CfgPIO ();

> AT91F_PIO_CfgPullup (AT91C_BASE_PIOB, AT91C_PB20_RK0);

> AT91F_SSC0_CfgPMC ();

> AT91C_BASE_SSC0->SSC_CR = AT91C_SSC_SWRST;

> AT91F_PDC_Close((AT91PS_PDC) &(AT91C_BASE_SSC0->SSC_RPR));

>

> AT91F_SSC_SetBaudrate ( AT91C_BASE_SSC0, MCK, SAMPLE_FREQ * HIGH_SPEED );

>

> /* Confige for ADS1278 frame-sync */

> AT91C_BASE_SSC0->SSC_RCMR = ( (( CKS_DIVIDED_CLOCK)& AT91C_SSC_CKS) |

> (( CKO_CONTINUOUS)& AT91C_SSC_CKO) |

> (( CKI_SAMPLE_FALLING_EDGE)& AT91C_SSC_CKI) |

> (( CKG_NO_CLOCK_GATE)& ((U32) 0x3 << 6)) |

> (( AT91C_SSC_START_RISE_RF)& AT91C_SSC_START) |

> (( STOP_RX)& AT91C_SSC_STOP) |

> (( PERIOD)& AT91C_SSC_PERIOD)

> );

> AT91C_BASE_SSC0->SSC_RFMR = ( ((RFMR_DATLEN)& AT91C_SSC_DATLEN) |

> ((RFMR_LOOP)& AT91C_SSC_LOOP) |

> ((RFMR_MSBF)& AT91C_SSC_MSBF) |

> ((RFMR_DATNB)& AT91C_SSC_DATNB) |

> ((RFMR_FSLEN)& AT91C_SSC_FSLEN) |

> ((RFMR_FSOS)& AT91C_SSC_FSOS)

> );

> /*----------------------------------------------------------

> Enable DMA transfer

> ----------------------------------------------------------*/

> AT91F_PDC_SetRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw1, BUF_SIZE);

> AT91F_PDC_SetNextRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw2, BUF_SIZE);

> AT91F_PDC_EnableRx (AT91C_BASE_PDC_SSC0); /* Enable the PDC feature */

> AT91F_SSC_EnableRx ( AT91C_BASE_SSC0 );

> }

> /*----------------------------------------------------------

> ----------------------------------------------------------*/

> int main ( void )

> {

>

> SSC_Configura();

>

> while(1)

> {

> AT91F_SSC_ReceiveFrame (AT91C_BASE_SSC0, (S8*)adc_raw1, BUF_SIZE,

> (S8*)adc_raw2, BUF_SIZE);



Now you're receiving 32 bytes to 1st buffer, then switching to the

next buffer, receiving 32 bytes to it, etc. So first 24 bytes in buffer 1

second 24 bytes block is spread into buffer 1 and 2(first 8 bytes in buffer 1

and last 16 bytes in buffer two), etc... So it's normal that every sample of

your any channel shifts 8 bytes left(thinking your adc_raw buffers as circular

buffers)



I may be wrong but this is what I see when I analyze your code. I hope this helps.

BTW, your ADC samples are not byte aligned, they are aligned on a 3 bytes boundary, so

receiving samples into an integer buffer will not work for all channels so easily.

Be careful for alignment errors. Turning on an extra status byte for each channel

on ADS1278 may help, though I don't know if it is possible. It was possible for ADS1258.



Regards,

Caglar




__._,_.___




















__,_._,___



(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )

Re: AT91SAM9260 and ADS1278 - AQ in random position in memory - Caglar Akyuz - May 14 8:35:41 2008

Alex Ruiz wrote:

> Caglar,
>
> Your feedback didn't help me much but it made me think more about what
> was going on.
>
If there were such thing, then guess I would be one of the best code-fiction
writers around :D

Caglar

------------------------------------



(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )