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Discussion Groups | AT91SAM ARM | Re: AW: TCM vs. internal SRAM
For users of the Atmel AT91SAM7 and AT91SAM9 ARM CPU chips. Atmel has taken a new direction by combining on chip flash and ram with the ARM CPU on a single die. This provides low cost devices for small systems using the ARM CPU. This group is to exchange information to help users get started and learn how to use the devices.
Re: AW: TCM vs. internal SRAM - 42Bastian - Mar 18 11:38:00 2008
Hi Bekir
> #define ITCM_BASE 0x100000 /* In memory map, I-TCM is located at the second MB, but I have a feeling like what I am doing here might not be correct */
> #define ITCM_SIZE (0x5 << 2) /* 16KB */
> #define ITCM_ENABLE 0x1
> #define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)
>
> MRC p15, 0, r1, c9, c1, 1
> ORR r1, r1, #ITCM_PATTERN
> MCR p15, 0, r1, c9, c1, 1
>
> And I am copying the IRQ handler code not the the internal SRAM, but to the second MB.
> But it stops at the first interrupt.
> Should I take another measure to enable TCM??
Yes. You need to enable it also in the controller but I do not know the
register by heart.
All I remember is that the order was important.
--
42Bastian
Note: SPAM-only account, direct mail to bs42@...
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
> #define ITCM_BASE 0x100000 /* In memory map, I-TCM is located at the second MB, but I have a feeling like what I am doing here might not be correct */
> #define ITCM_SIZE (0x5 << 2) /* 16KB */
> #define ITCM_ENABLE 0x1
> #define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)
>
> MRC p15, 0, r1, c9, c1, 1
> ORR r1, r1, #ITCM_PATTERN
> MCR p15, 0, r1, c9, c1, 1
>
> And I am copying the IRQ handler code not the the internal SRAM, but to the second MB.
> But it stops at the first interrupt.
> Should I take another measure to enable TCM??
Yes. You need to enable it also in the controller but I do not know the
register by heart.
All I remember is that the order was important.
--
42Bastian
Note: SPAM-only account, direct mail to bs42@...
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
AW: AW: TCM vs. internal SRAM - "ICLI, Bekir (EXT)" - Mar 19 9:15:56 2008
Thanks for the answers Bastian.
I hope there is someone who can explain this to me.
No matter when I read the TCM status from c0 (after or before enabling), it=
says always 0.
There are definitely somethings points I am missing here.
Mit freundlichem Gru=DF / Best regards
Bekir ICLI
-----Urspr=FCngliche Nachricht-----
Von: A...@yahoogroups.com [mailto:A...@yahoogroups.com] Im Auftrag vo=
n 42Bastian
Gesendet: Dienstag, 18. M=E4rz 2008 16:27
An: A...@yahoogroups.com
Betreff: Re: AW: [AT91SAM] TCM vs. internal SRAM
Hi Bekir
> #define ITCM_BASE 0x100000 /* In memory map, I-TCM is locat=
ed at the second MB, but I have a feeling like what I am doing here might n=
ot be correct */
> #define ITCM_SIZE (0x5 << 2) /* 16KB */
> #define ITCM_ENABLE 0x1
> #define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)
>=20
> MRC p15, 0, r1, c9, c1, 1=20=20=20=20=20=20=20
> ORR r1, r1, #ITCM_PATTERN=20
> MCR p15, 0, r1, c9, c1, 1=20
>=20
> And I am copying the IRQ handler code not the the internal SRAM, but to t=
he second MB.
> But it stops at the first interrupt.
> Should I take another measure to enable TCM??
Yes. You need to enable it also in the controller but I do not know the=20
register by heart.
All I remember is that the order was important.
--=20
42Bastian
Note: SPAM-only account, direct mail to bs42@...
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )
I hope there is someone who can explain this to me.
No matter when I read the TCM status from c0 (after or before enabling), it=
says always 0.
There are definitely somethings points I am missing here.
Mit freundlichem Gru=DF / Best regards
Bekir ICLI
-----Urspr=FCngliche Nachricht-----
Von: A...@yahoogroups.com [mailto:A...@yahoogroups.com] Im Auftrag vo=
n 42Bastian
Gesendet: Dienstag, 18. M=E4rz 2008 16:27
An: A...@yahoogroups.com
Betreff: Re: AW: [AT91SAM] TCM vs. internal SRAM
Hi Bekir
> #define ITCM_BASE 0x100000 /* In memory map, I-TCM is locat=
ed at the second MB, but I have a feeling like what I am doing here might n=
ot be correct */
> #define ITCM_SIZE (0x5 << 2) /* 16KB */
> #define ITCM_ENABLE 0x1
> #define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)
>=20
> MRC p15, 0, r1, c9, c1, 1=20=20=20=20=20=20=20
> ORR r1, r1, #ITCM_PATTERN=20
> MCR p15, 0, r1, c9, c1, 1=20
>=20
> And I am copying the IRQ handler code not the the internal SRAM, but to t=
he second MB.
> But it stops at the first interrupt.
> Should I take another measure to enable TCM??
Yes. You need to enable it also in the controller but I do not know the=20
register by heart.
All I remember is that the order was important.
--=20
42Bastian
Note: SPAM-only account, direct mail to bs42@...
------------------------------------
(You need to be a member of AT91SAM -- send a blank email to AT91SAM-subscribe@yahoogroups.com )