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Discussion Groups | 68HC12 | MC9S12DP256B and uCOS-II ROTS


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Join our technical discussions about Freescale Microcontrollers: M68HC12. (Freescale Semiconductor is a Subsidiary of Motorola).

MC9S12DP256B and uCOS-II ROTS - Salvador - Jan 23 0:58:00 2003


Hi,

Has anyone been able to port the uCOS-II ROTS to the MC9S12DP256B?
I don't have much experience with either product and I am having
problems understading where and how to initialize the interrupt vetor
table.

Any help or hints would be greatly appreciated.

As far as I can tell:

1) The vector table is loated at $FF00- $FFFF when using the chip in
single chip mode.

2) When using DBUG12 the vector table starts at $E300?

3) Where is the table located when using a debugger with a BDM
POD/probe ?????

4) How do I initialize the table? Is it enough to simply put the
address of my IRQ routine in each table entry OR do I also have to
put a JMP instruction in each table entry?

5) Can I use the SWI intruction anytime when using a)DBug12, b) BDM
POD/probe, and c) during regular single chip mode operation? Is SWI
mainly reserved for debugging purposes?

Thank you in advance.

/Salvador






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Re: MC9S12DP256B and uCOS-II ROTS - Stephen Trier - Jan 23 17:04:00 2003

Hi, Salvador,

I can't help you with the uCOS-II question, but maybe I can help you
with some of the others:

At 05:58 AM 1/23/03 -0000, Salvador <> wrote:
>1) The vector table is loated at $FF00- $FFFF when using the chip in
>single chip mode.

Correct. It may not fill that whole area depending on the HC12 variant
you are using.

>2) When using DBUG12 the vector table starts at $E300?

Yes, D-Bug12 emulates the vector table at another address. I don't know
what address that table has on a 9S12DP256, but $E300 sounds plausible.

>3) Where is the table located when using a debugger with a BDM
>POD/probe ?????

It's at the same address in both BDM ("special") and normal mode.

>4) How do I initialize the table? Is it enough to simply put the
>address of my IRQ routine in each table entry OR do I also have to
>put a JMP instruction in each table entry?

Each table entry contains the address of your interrupt or reset handler
Don't include a JMP instruction. With only two bytes per entry, there
is no room for it.

>5) Can I use the SWI intruction anytime when using a)DBug12, b) BDM
>POD/probe, and c) during regular single chip mode operation?

I don't know whether a resident D-Bug12 needs SWI. Otherwise, whether
or not BDM is active, the SWI instruction is available for your use.

>Is SWI mainly reserved for debugging purposes?

Nope! It's yours. You are free to use SWI for operating system calls, if
that's what you have in mind.

Stephen

--
Stephen Trier
Technical Development Lab
Cleveland FES Center / CWRU
/ KG8IH


______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!


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Re: MC9S12DP256B and uCOS-II ROTS - smedlytonker - Jan 26 21:35:00 2003

I am having the same problem as Salvador except that I have been
able to get UCOS-II running, but only when DBUG12 is running. You
were right about the location of the vector table while using
DBUG12. My problem is when their is no DBUG12 or boot loader. Every
interrupt vectors me to address 0. I deleted DBUG12 because it was
giving me trouble writing my UCOS port to flash and unintentionally
deleted the boot loader.

Again why would the following code vector me address 0?

--- In , Stephen Trier <sct@p...> wrote:
> Hi, Salvador,
>
> I can't help you with the uCOS-II question, but maybe I can help
you
> with some of the others:
>
> At 05:58 AM 1/23/03 -0000, Salvador <salramirez@u...> wrote:
> >1) The vector table is loated at $FF00- $FFFF when using the chip
in
> >single chip mode.
>
> Correct. It may not fill that whole area depending on the HC12
variant
> you are using.
>
> >2) When using DBUG12 the vector table starts at $E300?
>
> Yes, D-Bug12 emulates the vector table at another address. I
don't know
> what address that table has on a 9S12DP256, but $E300 sounds
plausible.
>
> >3) Where is the table located when using a debugger with a BDM
> >POD/probe ?????
>
> It's at the same address in both BDM ("special") and normal mode.
>
> >4) How do I initialize the table? Is it enough to simply put the
> >address of my IRQ routine in each table entry OR do I also have
to
> >put a JMP instruction in each table entry?
>
> Each table entry contains the address of your interrupt or reset
handler
> Don't include a JMP instruction. With only two bytes per entry,
there
> is no room for it.
>
> >5) Can I use the SWI intruction anytime when using a)DBug12, b)
BDM
> >POD/probe, and c) during regular single chip mode operation?
>
> I don't know whether a resident D-Bug12 needs SWI. Otherwise,
whether
> or not BDM is active, the SWI instruction is available for your
use.
>
> >Is SWI mainly reserved for debugging purposes?
>
> Nope! It's yours. You are free to use SWI for operating system
calls, if
> that's what you have in mind.
>
> Stephen
>
> --
> Stephen Trier
> Technical Development Lab
> Cleveland FES Center / CWRU
> sct@p... / KG8IH




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Re: MC9S12DP256B and uCOS-II ROTS - smedlytonker - Jan 26 21:59:00 2003

I forgot to post my example code

main()
{
__asm swi;
}

why does this vector to address 0 instead of address FFF6?

PS By the way I am using CodeWarrior using BDM (ICD-12)


______________________________
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Real-world software for real-time control. Details Here!


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Re: Re: MC9S12DP256B and uCOS-II ROTS - Stephen Trier - Jan 27 11:50:00 2003

At 02:59 AM 1/27/03 -0000, smedlytonker <> wrote:
>why does this vector to address 0 instead of address FFF6?

If the program counter is going to $0000 after the SWI, it most likely
means that FFF6:FFF7 contains $0000.

Where do you expect the SWI to take you? The address of that location
(the SWI handler) should be in FFF6:FFF7. FFF6:FFF7 is a pointer to the
handler, not the handler itself.

>PS By the way I am using CodeWarrior using BDM (ICD-12)

I'm unfamiliar with CodeWarrior, but if I'm not mistaken, it has some nice
syntax for loading the interrupt vector table. Perhaps someone else on the
list could help with that?

Stephen

--
Stephen Trier
Technical Development Lab
Cleveland FES Center / CWRU
/ KG8IH

______________________________
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!


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Re: MC9S12DP256B and uCOS-II ROTS - CW vector tables - christian_theiss_2003 - Jan 28 8:46:00 2003

Hi Salvador and altogether,

...let me introduce myself. I have just joined the HC12 group and was
following up the threads being around the last few days.
I am an embedded system developer as you could assume ;) and I am
working in the automotive area targeting also a HC(S)12 system as the
topic of this mailing list/group as far as I could follow the
threads... but my exact setup configuration in the very next
posting :)

But now to answer your CW dedicated vector table question please note
the following:

I) If you have a CW IDE as I have please look at the "\Application
Notes\HC12 <or similar target>" subdirectory derived from the program
directory of your installed Metrowerks CodeWarrior copy and look
through the AN2216.pdf application note "Software Development Using
Metrowerk's CodeWarrior", page 15-17 - the very first beginning for
SW/FW developers :) - to see that there are 2 different ways to
generate vector tables:

1 the "automatically" generated one(as I did 'cause I have only a few
vectors at the moment as I just started development :))

1.1 First of all you have to place the vector address(es) of your
interrupt service routine(s) as interrupt source channel(s) into the
build target dependent linker file as for ram.prm, flash.prm or
banked_flash.prm if you take the default one on a default project
being placed in \prm subdirectory of your project directory, for e.g.:

VECTOR ADDRESS 0xFFFE _Startup
VECTOR ADDRESS 0xFFCE _PORT_J_ISR
VECTOR ADDRESS 0xFFD6 _SCI0_ISR

--> now the linker knows you have some more routines to link against
your overall absolute binary image *.abs on a specific located
address as interrupt routines aren't at default exported as they need
to be placed in a non-banked page within the address map of the
MC9S12DP256B & derivatives as showed in the following section 1.2!

1.2 Secondly, you have to markup your ISR with an ANSI-C
standard "#pragma TRAP_PROC <your function>" in front of EACH ISR
function for being placed in a non-banked section and it should work!
The background for this is the non-standard variant to set
an "_interrupt" macro in front of the ISR as I have seen this at the
Imagecraft compiler's project conditionals... OK, I don't know
exactly this last item... 2. the manual one(to come if I will be using nearly all subsystems
interrupt-driven ...hopefully not... 'cause it's more convenient to
setup one vector table file as to give your linker file a bloat
extent for all your 64 vectors you would probably not all be using ;)

...as you look at page 15-17 you will also be able to use the
manually coded vector table being exported to your main application
project tree as outlined in this very helpful application note...

...hope I could give you some helpful advises... and please don't
hesitate to ask if it's still not working while trying out the above
steps...
Happy H(ack)CS12(ing),

Christian joining the HC(S)12 community(and hope to also get help
next in an upcoming posting!-)
--- In , "Salvador <salramirez@u...>"
<salramirez@u...> wrote:
>
> Hi,
>
> Has anyone been able to port the uCOS-II ROTS to the MC9S12DP256B?
> I don't have much experience with either product and I am having
> problems understading where and how to initialize the interrupt
vetor
> table.
>
> Any help or hints would be greatly appreciated.
>
> As far as I can tell:
>
> 1) The vector table is loated at $FF00- $FFFF when using the chip
in
> single chip mode.
>
> 2) When using DBUG12 the vector table starts at $E300?
>
> 3) Where is the table located when using a debugger with a BDM
> POD/probe ?????
>
> 4) How do I initialize the table? Is it enough to simply put the
> address of my IRQ routine in each table entry OR do I also have to
> put a JMP instruction in each table entry?
>
> 5) Can I use the SWI intruction anytime when using a)DBug12, b) BDM
> POD/probe, and c) during regular single chip mode operation? Is
SWI
> mainly reserved for debugging purposes?
>
> Thank you in advance.
>
> /Salvador
> salramirez@u...



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